Memory elements and cross point switches and arrays of same using nonvolatile nanotube blocks

ABSTRACT

Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of and claims priority under 35U.S.C. §120 to U.S. patent application Ser. No. 11/835,613, filed onAug. 8, 2007, entitled “MEMORY ELEMENTS AND CROSS POINT SWITCHES ANDARRAYS OF SAME USING NONVOLATILE NANOTUBE BL0CKS,” which claims thebenefit under 35 U.S.C. §119(e) of the following applications, theentire contents of which are incorporated herein by reference:

U.S. Provisional Patent Application No. 60/918,388, entitled “MemoryElements and Cross Point Switches and Arrays of Same Using NonvolatileNanotube Blocks,” filed on Mar. 16, 2007;

U.S. Provisional Patent Application No. 60/855,109, entitled“Nonvolatile Nanotube Blocks,” filed on Oct. 27, 2006;

U.S. Provisional Patent Application No. 60/840,586, entitled“Nonvolatile Nanotube Diode,” filed on Aug. 28, 2006;

U.S. Provisional Patent Application No. 60/836,437, entitled“Nonvolatile Nanotube Diode,” filed on Aug. 8, 2006;

U.S. Provisional Patent Application No. 60/836,343, entitled “ScalableNonvolatile Nanotube Switches as Electronic Fuse Replacement Elements,”filed on Aug. 8, 2006.

U.S. patent application Ser. No. 11/835,613 is a continuation-in-part ofand claims priority under 35 U.S.C. §120 to U.S. patent application Ser.No. 11/280,786, entitled “Two-Terminal Nanotube Devices And Systems AndMethods Of Making Same,” filed Nov. 15, 2005, the entire contents ofwhich are incorporated by reference, which claims the benefit under 35U.S.C. §119(e) of the following applications, the entire contents ofwhich are incorporated herein by reference:

U.S. Provisional Patent Application No. 60/692,891, entitled “ReversibleNanoswitch,” filed on Jun. 22, 2005;

U.S. Provisional Patent Application No. 60/692,918, entitled “NRAMNonsuspended Reversible Nanoswitch Nanotube Array,” filed on Jun. 22,2005;

U.S. Provisional Patent Application No. 60/692,765, entitled “EmbeddedCNT Switch Applications for Logic,” filed on Jun. 22, 2005;

U.S. Provisional Patent Application No. 60/679,029, entitled “ReversibleNanoswitch,” filed on May 9, 2005.

U.S. patent application Ser. No. 11/835,613 is also acontinuation-in-part of and claims priority under 35 U.S.C. §120 to U.S.patent application Ser. No. 11/274,967, entitled “Memory Arrays UsingNanotube Articles With Reprogrammable Resistance,” filed Nov. 15, 2005,the entire contents of which are incorporated by reference, which claimsthe benefit under 35 U.S.C. §119(e) of the following applications, theentire contents of which are incorporated herein by reference:

U.S. Provisional Patent Application No. 60/692,891, entitled “ReversibleNanoswitch,” filed on Jun. 22, 2005;

U.S. Provisional Patent Application No. 60/692,918, entitled “NRAMNonsuspended Reversible Nanoswitch Nanotube Array,” filed on Jun. 22,2005;

U.S. Provisional Patent Application No. 60/692,765, entitled “EmbeddedCNT Switch Applications for Logic,” filed on Jun. 22, 2005;

U.S. Provisional Patent Application No. 60/679,029, entitled “ReversibleNanoswitch,” filed on May 9, 2005.

U.S. patent application Ser. No. 11/835,613 is also acontinuation-in-part of and claims priority under 35 U.S.C. §120 to U.S.patent application Ser. No. 11/280,599, entitled “Non-Volatile ShadowLatch Using A Nanotube Switch,” filed Nov. 15, 2005, the entire contentsof which are incorporated by reference, which claims the benefit under35 U.S.C. §119(e) of the following applications, the entire contents ofwhich are incorporated herein by reference:

U.S. Provisional Patent Application No. 60/692,891, entitled “ReversibleNanoswitch,” filed on Jun. 22, 2005;

U.S. Provisional Patent Application No. 60/692,918, entitled “NRAMNonsuspended Reversible Nanoswitch Nanotube Array,” filed on Jun. 22,2005;

U.S. Provisional Patent Application No. 60/692,765, entitled “EmbeddedCNT Switch Applications for Logic,” filed on Jun. 22, 2005;

U.S. Provisional Patent Application No. 60/679,029, entitled “ReversibleNanoswitch,” filed on May 9, 2005.

U.S. patent application Ser. No. 11/835,613 is related to the followingapplications, the entire contents of which are incorporated byreference:

U.S. patent application Ser. No. (TBA), filed on Aug. 8, 2007, entitled“Nonvolatile Resistive Memories Having Scalable Two-Terminal NanotubeSwitches;”

U.S. patent application Ser. No. (TBA), filed on Aug. 8, 2007, entitled“Latch Circuits and Operation Circuits Having Scalable NonvolatileNanotube Switches as Electronic Fuse Replacement Elements;”

U.S. patent application Ser. No. (TBA), filed on Aug. 8, 2007, entitled“Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and SystemsUsing Same and Methods of Making Same;”

U.S. patent application Ser. No. (TBA), filed on Aug. 8, 2007, entitled“Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and SystemsUsing Same and Methods of Making Same;”

U.S. patent application Ser. No. (TBA), filed on Aug. 8, 2007, entitled“Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and SystemsUsing Same and Methods of Making Same;”

U.S. patent application Ser. No. (TBA), filed on Aug. 8, 2007, entitled“Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and SystemsUsing Same and Methods of Making Same;”

U.S. patent application Ser. No. (TBA), filed on Aug. 8, 2007, entitled“Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and SystemsUsing Same and Methods of Making Same;” and

U.S. patent application Ser. No. (TBA), filed on Aug. 8, 2007, entitled“Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and SystemsUsing Same and Methods of Making Same.”

BACKGROUND

1. Technical Field

The present application is generally related to the field of switchingdevices and memory elements that include nanotube elements.

2. Discussion of Related Art

Digital logic circuits are used in personal computers, portableelectronic devices such as personal organizers and calculators,electronic entertainment devices, and in control circuits forappliances, telephone switching systems, automobiles, aircraft and otheritems of manufacture. Digital logic circuits include logic and memoryfunctions that may be stand-alone or may be combined (integrated) on thesame chip. Ever-increasing amounts of logic and memory are required.

Important characteristics for logic circuit design are shorttime-to-market, brief error-free design cycles, and the ability tomodify logic functions in a field environment to better matchapplication requirements. Cross point switch matrices have been usefulin meeting such these requirements. However, cross point switch matrixdensities need to be higher and ease of integration needs to beimproved.

There is an ever-increasing demand for ever-denser memories that enablelarger memory functions, both stand alone and embedded, ranging from100's of kbits to memories in excess of 1 Gbit. These larger memoriesrequire increasingly higher densities, sold in increasing volumes, atlower cost per bit, operating at higher speed, and dissipating lesspower. These requirements challenging the semiconductor industry torapidly reduce geometries using improved process features. Increasedmemory density requires smaller cells which include smaller selecttransistors and smaller storage nodes. Power dissipation per bit isreduced by using smaller cell sizes.

Integrated circuits constructed from either bipolar or FET switchingelements are typically volatile. They only maintain their internallogical state while power is applied to the device. When power isremoved, the internal state is lost unless some type of non-volatilememory circuit, such as EEPROM (electrically erasable programmableread-only memory), is added internal or external to the device tomaintain the logical state. Even if non-volatile memory is utilized tomaintain the logical state, additional circuitry is necessary totransfer the digital logic state to the memory before power is lost, andto restore the state of the individual logic circuits when power isrestored to the device. Alternative solutions to avoid losinginformation in volatile digital circuits, such as battery backup, alsoadd cost and complexity to digital designs.

Devices have been proposed which use nanoscopic wires, such assingle-walled carbon nanotubes, to form crossbar junctions to serve asmemory cells. (See WO 01/03208, Nanoscopic Wire-Based Devices, Arrays,and Methods of Their Manufacture; and Thomas Rueckes et al., “CarbonNanotube-Based Nonvolatile Random Access Memory for MolecularComputing,” Science, vol. 289, pp. 94-97, 7 Jul. 2000.) Hereinafterthese devices are called nanotube wire crossbar memories (NTWCMs). Underthese proposals, individual single-walled nanotube wires suspended overother wires define memory cells. Electrical signals are written to oneor both wires to cause them to physically attract or repel relative toone another. Each physical state (i.e., attracted or repelled wires)corresponds to an electrical state. Repelled wires are an open circuitjunction. Attracted wires are a closed state forming a rectifiedjunction. When electrical power is removed from the junction, the wiresretain their physical (and thus electrical) state thereby forming anon-volatile memory cell.

U.S. Pat. No. 6,919,592, entitled “Electromechanical Memory Array UsingNanotube Ribbons and Method for Making Same” discloses, among otherthings, electromechanical circuits, such as memory cells, in whichcircuits include a structure having electrically conductive traces andsupports extending from a surface of a substrate. Nanotube ribbons thatcan electromechanically deform, or switch are suspended by the supportsthat cross the electrically conductive traces. Each ribbon includes oneor more nanotubes. The ribbons are typically formed from selectivelyremoving material from a layer or matted fabric of nanotubes.

For example, as disclosed in U.S. Pat. No. 6,919,592, a nanofabric maybe patterned into ribbons, and the ribbons can be used as a component tocreate non-volatile electromechanical memory cells. The ribbon iselectromechanically-deflectable in response to electrical stimulus ofcontrol traces and/or the ribbon. The deflected, physical state of theribbon may be made to represent a corresponding information state. Thedeflected, physical state has non-volatile properties, meaning theribbon retains its physical (and therefore informational) state even ifpower to the memory cell is removed. As disclosed in U.S. Pat. No.6,911,682, entitled “Electromechanical Three-Trace Junction Devices,”three-trace architectures may be used for electromechanical memorycells, in which the two of the traces are electrodes to control thedeflection of the ribbon.

The use of an electromechanical bi-stable device for digital informationstorage has also been suggested (See U.S. Pat. No. 4,979,149, entitled“Non-volatile Memory Device Including a Micro-Mechanical StorageElement”).

The creation and operation of bi-stable, nano-electro-mechanicalswitches based on carbon nanotubes (including mono-layers constructedthereof) and metal electrodes has been detailed in earlier patentapplications having a common assignee as the present application, forexample in the incorporated patent references listed below.

SUMMARY

The present invention provides non-volatile memory elements and crosspoint switches and arrays of same using nonvolatile nanotube elements.

Under one aspect, a covered nanotube switch includes: (a) a nanotubeelement including an unaligned plurality of nanotubes, the nanotubeelement having a top surface, a bottom surface, and a plurality of sidesurfaces; (b) first and second conductive terminals in contact with thenanotube element, wherein the first conductive terminal is disposed onand substantially covering the entire top surface of the nanotubeelement, and wherein the second conductive terminal contacts at least aportion of the bottom surface of the nanotube element; and (c) controlcircuitry in electrical communication with and capable of applyingelectrical stimulus to the first and second conductive terminals,wherein the nanotube element is capable of switching between a pluralityof electronic states in response to a corresponding plurality ofelectrical stimuli applied by the control circuitry to the first andsecond conductive terminals, and wherein, for each different electronicstate of the plurality of electronic states, the nanotube elementprovides an electrical pathway of corresponding different resistancebetween the first and second conductive terminals.

One or more embodiments include one or more of the following features.The first conductive terminal is also disposed on and substantiallycovers at least one side surface of the plurality of side surfaces. Thefirst conductive terminal is also disposed on and substantially coversthe plurality of side surfaces. An insulator layer in contact with thebottom surface of the nanotube element, the insulator layer and thesecond conductive terminal together substantially covering the entirebottom surface of the nanotube element. An insulator layer in contactwith at least one of the bottom surface of the nanotube element and oneof the side surfaces of the nanotube element. The insulator layerincludes one of SiO₂, SiN, and Al₂O₃. A passivation layer overlying atleast the first conductive terminal, the passivation layer substantiallysealing the first and second conductive terminals and the nanotubeelement to the environment. The passivation layer includes one of SiO₂,SiN, Al₂O₃, polyimide, phosphosilicate glass oxide, polyvinylidinefluoride, polypropylene carbonate, and polyethylene carbonate. Thesecond conductive terminal contacts substantially the entire bottomsurface of the nanotube element. The first and second conductiveterminals each include a conductive material independently selected fromthe group consisting of Ru, Ti, Cr, Al, Al(Cu), Au, Pd, Pt, Ni, Ta, W,Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu, TiPd, PbIn, TiW, RuN, RuO, TiN,TaN, CoSi_(x), and TiSi_(x).

Under another aspect, a covered nanotube switch includes: (a) a nanotubeelement including an unaligned plurality of nanotubes, the nanotubeelement having top and bottom surfaces; (b) first and second conductiveterminals in contact with the nanotube element and in spaced relation toeach other; (c) a first insulator layer in contact with the top surfaceof the nanotube element; (d) a second insulator layer in contact withthe bottom surface of the nanotube element, wherein the first and secondconductive terminals and the first and second insulator layers togethersubstantially surround the nanotube element; and (e) control circuitryin electrical communication with and capable of applying electricalstimulus to the first and second conductive terminals, wherein thenanotube element is capable of switching between a plurality ofelectronic states in response to a corresponding plurality of electricalstimuli applied by the control circuitry to the first and secondconductive terminals, and wherein, for each different electronic stateof the plurality of electronic states, the nanotube element provides anelectrical pathway of corresponding different resistance between thefirst and second conductive terminals.

One or more embodiments include one or more of the following features.At least a portion of the first insulator layer is separated from thetop surface of the nanotube element by a gap. At least a portion of thesecond insulator layer is separated from the bottom surface of thenanotube element by a gap. The first and second conductive terminalscontact the bottom surface of the nanotube element and wherein the firstinsulator layer contacts the entire top surface of the nanotube element.The first and second conductive terminals contact the top surface of thenanotube element. The first conductive terminal contacts the bottomsurface of the nanotube element and the second conductive terminalcontacts the top surface of the nanotube element. The first and secondinsulator layers each include an insulative material independentlyselected from the group consisting of SiO₂, SiN, and Al₂O₃. The firstand second conductive terminals each include a conductive materialindependently selected from the group consisting of Ru, Ti, Cr, Al,Al(Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu,TiPd, PbIn, TiW, RuN, RuO, TiN, TaN, CoSi_(x), and TiSi_(x).

Under another aspect, a covered nanotube switch includes: (a) a nanotubeelement including an unaligned plurality of nanotubes, the nanotubeelement having top and bottom surfaces; (b) first and second conductiveterminals in contact with the nanotube element and in spaced relation toeach other; (c) a first insulator layer arranged over and in spacedrelation to the top surface of the nanotube element; (d) a secondinsulator layer arranged under and in spaced relation to the bottomsurface of the nanotube element, wherein the first and second conductiveterminals and the first and second insulator layers togethersubstantially surround the nanotube element; and (e) control circuitryin electrical communication with and capable of applying electricalstimulus to the first and second conductive terminals, wherein thenanotube element is capable of switching between a plurality ofelectronic states in response to a corresponding plurality of electricalstimuli applied by the control circuitry to the first and secondconductive terminals, and wherein, for each different electronic stateof the plurality of electronic states, the nanotube element provides anelectrical pathway of corresponding different resistance between thefirst and second conductive terminals.

One or more embodiments include one or more of the following geatures.The first and second insulator layers each include an insulativematerial independently selected from the group consisting of SiO₂, SiN,and Al₂O₃. The first and second conductive terminals each include aconductive material independently selected from the group consisting ofRu, Ti, Cr, Al, Al(Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb,Sn, TiAu, TiCu, TiPd, PbIn, TiW, RuN, RuO, TiN, TaN, CoSi_(x), andTiSi_(x).

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIGS. 1A-1C are perspective drawings of an embodiment of a two terminalnonvolatile nanotube switch (NV NT switch) with bottom contact locationson each end, and two terminal nonvolatile nanotube block switches (NV NTblock switches) with combined top/side and bottom contact locations andanother with top and bottom contact locations.

FIG. 2A illustrates an embodiment of a NV NT switch in an essentiallyhorizontal orientation with two bottom contact terminals, each onopposite ends of a patterned nanotube channel element.

FIG. 2B illustrates an SEM view of an exemplary nonvolatile nanotubeswitch similar to the nonvolatile nanotube switch embodiment illustratedin FIG. 2A.

FIG. 2C illustrates the results of cycling data for an exemplarynonvolatile nanotube switch similar to FIG. 2B.

FIG. 3 illustrates an embodiment of a NV NT switch in an essentiallyhorizontal orientation with two bottom contact terminals, each onopposite ends of a patterned nanotube channel element, in which theswitch channel length is less than the spacing between contactterminals.

FIG. 4A illustrates an embodiment of a two terminal NV NT block switchof mixed vertical and horizontal orientation, with a bottom contactterminal to a nonvolatile nanotube block (NV NT block) and a combinedtop and side contact terminal to the NV NT block with an essentiallyhorizontal extension to a second bottom contact terminal.

FIG. 4B illustrates the results of cycling data for an exemplarynonvolatile nanotube block switch similar to FIG. 4B.

FIG. 5A illustrates an embodiment having a pair of two terminal NV NTblock switches of vertical orientation, with a bottom contact terminaland a top contact terminal to a nonvolatile nanotube block (NV NTblock).

FIG. 5B illustrates the results of cycling data for an exemplarynonvolatile nanotube block switch similar to FIG. 5A.

FIG. 6A illustrates the NV NT switch embodiment of FIG. 2A with theaddition of a passivation layer.

FIG. 6B illustrates the NV NT switch embodiment of FIG. 2A with theaddition of two passivation layers.

FIG. 6C illustrates the NV NT switch embodiment of FIG. 2A with theaddition of a passivation layer and a gap region above the patternednanotube element.

FIG. 6D illustrates the NV NT switch embodiment of FIG. 2A with theaddition of a passivation layer and gap regions above and below thepatterned nanotube element.

FIG. 7A illustrates the NV NT switch embodiment of FIG. 3 with theaddition of a passivation layer.

FIG. 7B illustrates the NV NT switch embodiment of FIG. 3 with theaddition of a passivation layer and a gap region above the channellength portion of the patterned nanotube element.

FIG. 8A illustrates the NV NT block switch embodiment of FIG. 4A withthe addition of a passivation layer.

FIG. 8B illustrates the NV NT block switch embodiment of FIG. 4A withthe addition of a passivation layer and a gap region adjacent side facesof the nonvolatile nanotube block region.

FIG. 8C illustrates an embodiment having a pair of two terminal NV NTblock switches of vertical orientation, with a bottom contact terminaland a top contact terminal to a nonvolatile nanotube block (NV NTblock), in which the top contact terminal is extended to include contactto all sides of the nonvolatile nanotube block.

FIG. 8D is a summary of the embodiments of NV NT switches and NV NTblock switches described in FIGS. 2A-8C that may be used as nonvolatilenanotube storage nodes in memory array cells.

FIG. 9A illustrates an embodiment of a memory element schematic that mayuse nonvolatile nanotube switches or nonvolatile nanotube block switchesas nonvolatile nanotube storage nodes for memory element cells.

FIG. 9B illustrates a layout of an embodiment of a 16 bit memory arraythat includes NMOS FET select transistors and CMOS buffer and controlcircuits.

FIG. 10A shows a top SEM image of an exemplary fabricated 16 bit memoryarray region that corresponds to the layout of FIG. 9B and showsnonvolatile nanotube storage nodes formed using nonvolatile nanotubeblock switches.

FIG. 10B shows a tilt angle SEM image of one of the exemplarynonvolatile nanotube block switches shown in of FIG. 10A.

FIG. 11A shows test results of write 0 and write 1 memory operationsperformed on the exemplary 16 bit memory array illustrated in FIGS.9A-10B.

FIG. 11B shows a schmoo plot write 0 and write 1 operating voltages forindividual bit (cell) locations in the exemplary 16 bit memory arrayillustrated in FIGS. 9A-10B.

FIG. 11C shows another schmoo plot of write 0 and write 1 operatingvoltages for individual bit (cell) locations in the exemplary 16 bitmemory array illustrated in FIGS. 9A-10B.

FIG. 12A illustrates a top view of an embodiment of four memory arraycells with nonvolatile nanotube switches used as nonvolatile nanotubestorage nodes and formed on the top surface of the cell region.

FIG. 12B illustrates a cross section of the memory array cell embodimentillustrated in FIG. 12A.

FIG. 13A illustrates a top view of an embodiment of four memory arraycells with top/side and bottom contact terminal-type nonvolatilenanotube block switches used as nonvolatile nanotube storage nodes andformed on the top surface of the cell region.

FIG. 13B illustrates a cross section of the memory array cell embodimentillustrated in FIG. 13A.

FIG. 14A illustrates a top view of an embodiment of four memory arraycells with top and bottom contact terminal-type nonvolatile nanotubeblock switches used as nonvolatile nanotube storage nodes and formed onthe top surface of the cell region.

FIG. 14B illustrates a cross section of the memory array cell embodimentillustrated in FIG. 14A.

FIG. 15 illustrates a cross section of an embodiment of memory arraycells with top and bottom contact terminal-type enclosed nonvolatilenanotube block switches used as nonvolatile nanotube storage nodes andformed on the top surface of the cell region.

FIG. 16A illustrates a top view of an embodiment of four memory arraycells with nonvolatile nanotube switches used as nonvolatile nanotubestorage nodes and integrated in the cell region in proximity to acorresponding select transistor and below the bit line.

FIG. 16B illustrates a cross section of the memory array cell embodimentillustrated in FIG. 16A.

FIG. 17A illustrates a top view of an embodiment of four memory arraycells with top/side and bottom contact terminal-type nonvolatilenanotube block switches used as nonvolatile nanotube storage nodes andintegrated in the cell region in proximity to a corresponding selecttransistor and below the bit line.

FIG. 17B illustrates a cross section of the memory array cell embodimentillustrated in FIG. 17A.

FIG. 18A illustrates a top view of an embodiment of four memory arraycells with top and bottom contact terminal-type nonvolatile nanotubeblock switches used as nonvolatile nanotube storage nodes and integratedin the cell region in proximity to a corresponding select transistor andbelow the bit line;

FIG. 18B illustrates a cross section of the memory array cell embodimentillustrated in FIG. 18A.

FIG. 19 illustrates a cross section of an embodiment of memory arraycells with top and bottom contact terminal-type enclosed nonvolatilenanotube block switches used as nonvolatile nanotube storage nodes andintegrated in the cell region in proximity to a corresponding selecttransistor and below the bit line.

FIG. 20A illustrates a cross section of an embodiment of memory arraycells with top and bottom contact terminal-type nonvolatile nanotubeblock switches used as nonvolatile nanotube storage nodes and integratedin the cell region in proximity to a corresponding select transistor andpositioned between a bit line contact and a drain of a correspondingselect transistor.

FIG. 20B shows a comparison of estimated cell areas as a function of thetype of nonvolatile nanotube storage node selected and the integrationmeans used, according to some embodiments.

FIG. 21 illustrates a cross section of an embodiment of a cross pointswitch formed using a nonvolatile nanotube switch in an essentiallyhorizontal orientation with a first center-region contact terminal and asecond “picture frame” contact terminal surrounding the first contact.

FIGS. 22A-22C illustrate a plan view and two corresponding crosssections of embodiments of cross point switches formed using a firsttype of top and bottom contact terminal nonvolatile nanotube blockswitches.

FIG. 22D shows an embodiment nonvolatile electrically programmed wirerouting connections corresponding to various ON and OFF combination ofnonvolatile nanotube block switches illustrated in FIGS. 22A-22C.

FIGS. 23A-23C illustrate a plan view and two corresponding crosssections of embodiments of cross point switches formed using a secondtype of top and bottom contact terminal nonvolatile nanotube blockswitches.

DETAILED DESCRIPTION

Embodiments of the invention provide memory elements and crosspointswitches and arrays of same using non-volatile nanotube blocks. Thememory cells and cross point switches include two-terminal nanotubeswitches, which include a nanotube element such as a nanotube block, inelectrical communication with two terminals. The switches are capable ofrepeated toggling between first and second states in response toelectrical stimulus at the two terminals, and thus are capable ofstoring a memory state or of providing a reprogrammable electricalconnection. The use of nanotube “blocks,” as contrasted with relativelythin (e.g., 0.5-10 nm) nanotube films, enables the fabrication ofrelatively high density memory and cross point switch arrays.

Some embodiments provide 2-D cell structures and enhanced 3-D cellstructures that enable dense nonvolatile memory arrays that include twoterminal nonvolatile nanotube storage nodes. The nodes include 2-Dnanotube switches referred to as nonvolatile nanotube switches (NV NTswitches) and/or 3-D nanotube switches referred to as nonvolatilenanotube block switches (NV NT block switches). The nodes also includecorresponding select transistors such as NMOS FETs (NFETs) that canwrite logic 1 and 0 states for multiple cycles, read stored logicstates, and hold logic states without power applied to the memory node.Some embodiments are scalable to large memory array structures and/orare compatible with CMOS circuit manufacture. While some embodimentscombine NMOS FETs with carbon nanotubes, it should be noted that basedon the principle of duality in semiconductor devices, PMOS FETs mayreplace NMOS FETs, along with corresponding changes in he polarity ofapplied voltages. It should also be noted that two terminal NV NT switchand NV NT block switch operation is independent of the current flowdirection through the nanotube and independent of the voltage polarityapplied to the respective ends (terminals) of the nanotube. It should befurther noted that a CMOS select device consisting of both NFET and PFETdevices may also be used instead of NMOS or PFET FET select transistors.

3-D NV NT block switches may be used as nonvolatile nanotube storagenodes in memory cells and as nonvolatile cross point switches in crosspoint switch matrix applications. In some embodiments, NV NT blockswitches may be as small as F×F on each side, where F is a minimumtechnology node dimension, as described in greater detail in U.S. PatentApplication No. (TBA), entitled “Nonvolatile Nanotube Diodes andNonvolatile Nanotube Blocks and Systems Using Same and Methods of MakingSame,” filed concurrently herewith.

It should be noted that nanotube-based nonvolatile memory arrays mayalso be configured as NAND and NOR arrays in PLA, FPGA, and PLDconfigurations, and that wire routing may also be configured usingnanotube-based nonvolatile cross point switches in cross point switchmatrices. Field programmable logic may be reconfigured multiple-timesusing a combination of nanotube-based nonvolatile memory arrays andcross point switch matrices to form stand-alone and embedded logicfunctions as well.

2-Dimensional (2-D) Horizontally-Oriented NV NT Switches and3-Dimensional (3-D) NV NT Block Switches

Examples of two-terminal 2-D nonvolatile nanotube switches (NV NTswitches) and two terminal 3-D nonvolatile nanotube block switches (NVNT block switches) are described in corresponding Figures and aresummarized in FIG. 8D, which is described further below. NV NT switchesor NV NT block switches may be formed at or near the top surface ofmemory arrays for ease of integration, or may be formed in cells closeto select transistors for high density (small footprint) as describedfurther below.

For ease of integration, memory cells may use nonvolatile nanotubestorage nodes with NV NT switches or NV NT block switches formed(fabricated) at or near a top surface above substantially pre-wiredmemory cells in which select transistors (typically NFETs) are connectedto array word lines (WLs) and bit lines (BLs). A stud interconnects thesource of the NFET select transistor to a first terminal of a NV NTswitch or NV NT block switch, while a second terminal is connected to areference array line also referred to as a secondary word line (WWL).

NV NT switches or NV NT block switches at or near the top surface ofmemory arrays facilitate nanotube switch integration because nearly allgrowth, deposition, and etch steps required by the semiconductorstructure have been completed prior to nanotube deposition andpatterning. Integrating nanotube switch structures near the end of thefabrication cycle enables rapid sample preparation since the memoryarrays may be conventionally pre-formed to the stage where only nanotubeswitch formation is needed to complete fabrication. However, in someembodiments, memory cell areas may be substantially larger (50 to 100%or more) in area than the minimum size capable of fabrication using agiven technology node F, for example in embodiments where bit lines(BLs) are placed adjacent to NFET select devices instead of over selectdevices to enable a stud connection between a source of the NFET selecttransistor and a corresponding switch terminal that is placed above thebit line array in the integrated structure.

NV NT switches or NV NT block switches at or near the top surface ofmemory arrays may be left unpassivated and may be hermetically sealed ina package, tested under typical conditions, and also evaluated fortolerance to harsh environments such as high temperatures and highradiation. Examples of unpassivated switches are illustrated in FIGS.2A, 3, and 4A described further below.

NV NT switches or NV NT block switches at or near the top surface ofmemory arrays may be passivated and packaged using conventionalpackaging means. Such passivated packaged chips may be tested undertypical conditions and also evaluated for tolerance to harshenvironments such as high temperatures and high radiation. Examples ofpassivated switches are illustrated in FIGS. 5A, 6A-6D, 7A-7B, 8A-8C asdescribed further below.

Passivated NV NT switches or NV NT block switches may also be integratednear an NFET select transistor, below the bit line, to achieve densememory cells. NV NT block switches with top and bottom contacts, such asillustrated in FIG. 5A, may be integrated in memory cells that are,e.g., 6-8F² in density, where F is a minimum technology node. Memorycell size (footprint) estimates based on the nanotube switchessummarized in FIG. 8D are described in FIG. 20B, as described in greaterdetail below.

2-D NV NT Switch and 3D NV NT Block Switch Structures

FIGS. 1A-1C illustrate perspective drawings of a thin nonvolatilenanotube element (NV NT element) and thicker nonvolatile nanotubeelements referred to a nonvolatile nanotube blocks (NV NT blocks) withvarious contact locations. The combination of NV NT elements andcontacts form two dimensional (2-D) NV NT switches and the combinationof NV NT blocks and contacts form three dimensional (3-D) NV NT blockswitches as illustrated in FIGS. 1A-1C. 3-D NV NT block switches may beused instead of NV NT switches as nonvolatile nanotube storage nodes (NVNT storage nodes) in memory array cells as well as cross point switchesfor fabrication advantages and denser memory cell and cross point switcharrays as illustrated further below. NV NT switches and NV NT blockswitches illustrated in FIGS. 1A-1C are an exemplary subset of possibleswitch configurations, some embodiments of which are described in, e.g.,U.S. patent application Ser. No. (TBA), entitled “Nonvolatile NanotubeDiodes and Nonvolatile Nanotube Blocks and Systems Using Same andMethods of Making Same,” filed concurrently herewith.

NV NT switch 1000A illustrated in perspective drawing in FIG. 1A shows aNV NT switch with relatively thin (e.g., about 0.5 nm to less than 10nm) nonvolatile nanotube element 1005 and bottom contact locations 1010and 1015. Contact locations illustrate where terminals (not shown)contact the surface of nanotube element 1005 as described further belowand in U.S. patent application Ser. No. 11/280,786.

NV NT block switch 1000B illustrated in perspective drawing in FIG. 1Bshows a NV NT block switch with NV NT block 1020 (e.g., typically 10 nmor greater in any given dimension) with a bottom contact location 1030and a top/side contact location 1025 including top contact location1025-2 and side contact location 1025-1. Edges of bottom contactlocation 1030 and side contact location 1025-1 are separated by anoverlap distance L_(OL). Contact locations illustrate where terminals(not shown) contact the surface of NV NT block 1020 as described furtherbelow and in U.S. patent application Ser. No. (TBA), entitled“Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and SystemsUsing Same and Methods of Making Same,” filed concurrently herewith.

NV NT block switch 1000C illustrated in perspective drawing in FIG. 1Cshows a NV NT block switch with NV NT block 1035 (e.g., 10 nm or greaterin any given dimension) with a bottom contact location 1040 and a topcontact location 1045. Contact locations illustrate where terminals (notshown) contact the surface of NV NT block 1035 as described furtherbelow and in U.S. patent application Ser. No. (TBA), entitled“Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and SystemsUsing Same and Methods of Making Same,” filed concurrently herewith. 3-DNV NT block switch 1000C occupies a relatively small area (has arelatively small footprint) relative to other embodiments of 3-D NV NTblock switches and 2-D NV NT switches.

NV NT switch 1000A corresponds to NV NT switch 2000 illustrated in FIG.2A further below, where nanotube element 1005A corresponds to nanotubeelement 2035, contact location 1010 corresponds to the location ofcontact terminal 2010, and contact location 1015 corresponds to thelocation of contact terminal 2015.

FIG. 2A, described in more detail in U.S. patent application Ser. No.11/280,786, illustrates NV NT Switch 2000 including patterned nanotubeelement 2035 on insulator 2030, which is on the surface of combinedinsulator and wiring layer 2020, which is supported by substrate 2025.Patterned nanotube element 2035 is a nanofabric on a planar surface, andpartially overlaps and contacts terminals (conductive elements) 2010 and2015. Contact terminals 2010 and 2015 are deposited and patterneddirectly onto combined insulator and wiring layer 2020, which is onsubstrate 2025, prior to patterned nanotube element 2035 formation. Thenonvolatile nanotube switch channel length L_(SW-CH) is the separationbetween contact terminals 2010 and 2015. Substrate 2025 may be aninsulator such as ceramic or glass, a semiconductor, or an organic rigidor flexible substrate. Substrate 2025 may be also be organic, and may beflexible or stiff. Insulators 2020 and 2030 may be SiO₂, SiN, Al₂O₃, oranother insulator material. Terminals 2010 and 2015 may be formed usinga variety of contact and interconnect elemental metals such as Ru, Ti,Cr, Al, Al(Cu), Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, as well asmetal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, other suitableconductors, or conductive nitrides, oxides, or silicides such as RuN,RuO, TiN, TaN, CoSi_(x) and TiSi_(x).

FIG. 2B, described in more detail in U.S. patent application Ser. No.11/280,786, illustrates an SEM image of a nonvolatile nanotube switch2000′ prior to passivation and corresponds to nonvolatile nanotubeswitch 2000 in the cross sectional drawing in FIG. 2A. Nonvolatilenanotube switch 2000′ includes nanofabric element 2035′, contactterminals 2010′ and 2015′ corresponding to contact terminals 2010 and2015, respectively, and an insulator 2020′ corresponding to insulatorand wiring layer 2020. Exemplary nonvolatile nanotube switches such asswitch 2000′ have been fabricated with channel lengths L_(CHANNEL) inthe range of 250 nm to 22 nm thereby reducing nonvolatile nanotubeswitch size and lowering programming voltages, as described in moredetail in U.S. patent application Ser. No. 11/280,786, although othersuitable channel lengths can be used.

Laboratory testing of individual nonvolatile nanotube switches,described in more detail in U.S. patent application Ser. No. 11/280,786illustrates that nonvolatile nanotube switches such as switch 2000illustrated in a cross sectional drawing in FIG. 2A and corresponding toSEM micrograph of NV NT switch 2000′ illustrated in FIG. 2B has beencycled more than 50 million times between ON and OFF resistance statesas illustrated by graph 2050 in FIG. 2C. The conducting (ON) stateresistance is typically in the range of 10 kOhms to 50 kOhms, while thenonconducting (OFF) state resistance typically exceeds 1 GOhm, for agreater than five orders of magnitude separation of resistance valuesbetween conducting and nonconducting ON and OFF switch states,respectively. Testing of individual nonvolatile nanotube switches withshorter channel lengths, 50 nm for example, has resulted in lower write0 and write 1 voltage levels such as 4-5 volts instead of 8 to 10 voltsas illustrated in U.S. patent application Ser. No. 11/280,786.

FIG. 3 illustrates NV NT Switch 3000, a modification of NV NT switch2000 illustrated in FIG. 2A, including patterned nanotube element 3045supported by and in contact with contact terminals 3010 and 3015,contact terminal extension 3040 in physical and electrical contact withterminal 3010, and insulator 3035. Insulator 3042 completes theplanarized structure but is typically not in contact with patternednanotube element 3045. NV NT switch 3000 has approximately the sameoverall dimensions as NV NT switch 2000, except that insulators 3030 and3035 and extended contact terminal 3040 have been added to the basic NVNT switch 2000 structure using known preferred methods of fabrication toreduce NV NT switch 3000 channel length to shorter L_(SW-CH) asillustrated in FIG. 3. Shorter L_(SW-CH) channel length may reduce NV NTswitch 3000 operating voltage, as described in U.S. patent applicationSer. No. 11/280,786, because L_(SW-CH) length may be in the 5 to 50 nmlength range, for example, while contact terminals 3010 and 3015 may beseparated by 150 to 250 nm, for example. L_(SW-CH) length is determinedin part by the thickness of insulator 3035 as deposited on exposed upperregions of contact terminals 3010 and 3015 using known preferredsidewall spacer methods, such as those described in prior art U.S. Pat.No. 4,256,514 the entire contents of which are incorporated herein byreference. Exposed upper regions of contact terminals 3010 and 3015,between the top surface 3030′ of insulator 3030 and the coplanar topsurfaces of contact terminals 3010 and 3015, may be in the range of 10to 500 nm, for example. The top surface 3030′ of insulator 3030 may beformed by preferred industry methods of selective directional etch ofinsulator 3030 to a desired depth below the top surface of coplanarcontact terminals 3010 and 3015. Insulator 3030 and contact terminals3010 and 3030 are in contact with insulator and wiring layer 3020, whichis on substrate 3025.

Insulator 3035 is deposited using known preferred industry methods to athickness corresponding to a desired switch channel length L_(SW-CH)such as 5 to 50 nm, for example, and then patterned using preferredmethods.

Next, preferred methods deposit a conductor layer, and preferred methodssuch as chemical-mechanical polishing (CMP) are applied to combinedinsulator and conductor layer, such as those described in prior art U.S.Pat. No. 4,944,836 the entire contents of which are incorporated hereinby reference. At this point in the process, L_(SW)-_(CH) is defined asshown in FIG. 3, contact terminal 3015 and contact terminal 3010 incontact with contact terminal extension 3040 are also defined.

Next, insulator 3042 is formed using preferred methods of deposition andplanarization. Then, preferred methods pattern nanotube element 3045 asdescribed in incorporated patent applications.

Substrate 3025 may be an insulator such as ceramic or glass, asemiconductor, or an organic rigid or flexible substrate. Substrate 3025may be also be organic, and may be flexible or stiff. Insulators 3020,3030, 3035, and 3042 may be SiO₂, SiN, Al₂O₃, or another insulatormaterial. Contact terminals 3010 and 3015 and contact terminal extension3040 may be formed using a variety of contact and interconnect elementalmetals such as Ru, Ti, Cr, Al, Al(Cu), Au, Pd, Ni, W, Cu, Mo, Ag, In,Ir, Pb, Sn, as well as metal alloys such as TiAu, TiCu, TiPd, PbIn, andTiW, other suitable conductors, or conductive nitrides, oxides, orsilicides such as RuN, RuO, TiN, TaN, CoSi_(x) and TiSi_(x).

NV NT switches 2000 and 3000 are illustrated without an overlyinginsulating protective layer. If NV NT switches are formed on the toplayer of a semiconductor chip, then no insulation is required for chipoperation. However, chips typically are mounted in hermetically sealedpackages to ensure protection from mechanical handling and environmentalcontamination and moisture. If NV NT switches are to be integratedcloser to the semiconductor substrate, or not hermetically sealed, thenNV NT switches may be protected using insulating layers as describedfurther below with respect to FIGS. 5A, 6A-6D, 7A, 7B, and 8A-8C.

FIG. 4A, described in more detail in U.S. Provisional Patent ApplicationNo. U.S. Patent Application No. (TBA), entitled “Nonvolatile NanotubeDiodes and Nonvolatile Nanotube Blocks and Systems Using Same andMethods of Making Same,” filed concurrently herewith, illustrates a NVNT block switch 4000 corresponding to 3-D NV NT block switch 1000Billustrated in FIG. 1B. Switch 4000 occupies approximately the same areaas NV NT switches 2000 and 3000. NV NT block switch 4000 also featuresNV NT block overlap length L_(OL) which is determined by the separationbetween bottom contact terminal 4015 and an edge of NV NT block 4035. NVNT block switch 4000 includes a combination of side/top contact 4040formed by side surface contact 4040A and top surface contact 4040B andbottom surface contact 4042 formed by contact terminal 4015. Bottomsurface contact 4042 corresponds to bottom surface contact location 1030in NV NT block switch 1000B illustrated in perspective drawing in FIG.1B; side/top surface contact 4040 corresponds to top/side surfacecontact location 1025, top surface contact 4040B corresponds to topsurface contact location 1025-2; side surface contact 4040A correspondsto side surface location 1025-1; and NV NT block 4035 corresponds to NVNT block 1020. An effective overlap length L_(OL) is the distancebetween the edges of bottom surface contact 4042 and side/top surfacecontact 4040 described further below. Contact terminal 4010 is connectedto side/top surface contact 4040 by conductor 4045. Preferred methods offabrication may be used to simultaneously deposit and pattern conductor4045 and surface contact 4040, thereby forming combinedconductor/contact 4045/4040 interconnect means. NV NT block sidesurfaces may be partially defined by preferred methods of directionaletching the exposed portions of the nanotube block fabric using combinedconductor/contact 4045/4040 as a mask. NV NT block 4035 side surface4043 (and two other sides not visible in FIG. 4A) are exposed. Methodsof etching nanotube fabric layers are described in the incorporatedpatent references.

Contact terminals 4010 and 4015 are deposited and patterned directlyonto combined insulator and wiring layer 2020, which is on substrate4025, prior to patterned nanotube block 4035 formation. Substrate 4025may be an insulator such as ceramic or glass, a semiconductor, or anorganic rigid or flexible substrate. Substrate 4025 may be also beorganic, and may be flexible or stiff. Insulators 2020 and 4030 may beSiO₂, SiN, Al₂O₃, or another insulator material. Terminals 4010 and 4015may be formed using a variety of contact and interconnect elementalmetals such as Ru, Ti, Cr, Al, Al(Cu), Au, Pd, Ni, W, Cu, Mo, Ag, In,Ir, Pb, Sn, as well as metal alloys such as TiAu, TiCu, TiPd, PbIn, andTiW, other suitable conductors, or conductive nitrides, oxides, orsilicides such as RuN, RuO, TiN, TaN, CoSi_(x) and TiSi_(x).

Laboratory ON/OFF switching test results of an exemplary nonvolatilenanotube block switch corresponding to NV NT block switch 4000 aredescribed with respect to graph 4500 illustrated in FIG. 4B, where write0 corresponds to erase and results in a high resistance OFF state, andwrite 1 corresponds to program and results in a low resistance ON state.Test conditions and results are described in more detail in theincorporated patent references. Graph 4500 illustrates results ofelectrical tests that apply one write 0 voltage pulse of 6 volts, onewrite 1 voltage pulse of 6 V, and measure ON resistance at each ON/OFFcycle for 100 cycles. ON resistance values 4555 are typically in the 120kOhm to 1 MOhm range and OFF resistance values 4560 are typically above100 MOhms with most values above 1 GOhms. In two cases, ON resistancevalues 4565 exceeded 1 GOhm indicating failure to switch to the ONstate.

FIG. 5A illustrates two identical memory cells, cell 1 and cell 2, of a3-D diode-steering memory array described further in U.S. patentapplication Ser. No. (TBA), entitled “Nonvolatile Nanotube Diodes andNonvolatile Nanotube Blocks and Systems Using Same and Methods of MakingSame,” filed concurrently herewith. Cell 1 (identical to cell 2)includes steering diode 5010 with one terminal in contact with NV NTblock switch 5005 at bottom surface contact terminal 5020, and anotherdiode 5010 terminal in contact with array wiring conductor 5015. NV NTblock switch 5005 top contact 5040 is in contact with array wiringconductor 5050. NV NT block switch 5005 includes top contact 5040 incontact with NV NT block 5030 and bottom contact 5020 in contact with NVNT block 5030. NV NT block switch 5005 is embedded in dielectric 5060.NV NT block switch 5005 is relatively dense (occupies a relatively smallfootprint) because top and bottom contacts and NV NT block 5030 sidesurfaces can be defined by self-aligned trench preferred methods offabrication described further in the incorporated patent references andmay be used to form minimum NV NT storage node dimensions of F×F. WhileNV NT block switch 5005 is illustrated as integrated with diode 5010select (steering) devices, NV NT block switch 5005 may be combined withNFET select devices to form relatively dense memory arrays as describedfurther below with respect to FIGS. 18A-18C for example.

NV NT block switch 1000C illustrated further above in perspectivedrawing FIG. 1C illustrates NV NT block 1035 corresponding to NV NTblock 5030 illustrated in FIG. 5A. Bottom contact location 1040corresponds to bottom contact 5020 and top contact location 1045corresponds to top contact 5040.

The lateral dimensions of NV NT block switch 5010 may be as small asminimum dimensions F×F. NV NT block 5030 lateral dimensions may belarger than the minimum dimension F; the NV NT block 5030 sidedimensions need not be equal. Note also that the vertical (thickness)dimension of NV NT block switch 5010, as well as the other NV NT blockswitches described herein, is generally unconstrained by the minimumdimension F provided by the technology node. Instead, the vertical(thickness) dimension is related to the thickness of the nanotubefabric, which can be selected, e.g., to be sufficiently thick tosubstantially inhibit electrical contact between contacts 5020 and 5040,as described in greater detail in U.S. Patentp application Ser. No.(TBA), entitled “Nonvolatile Nanotube Diodes and Nonvolatile NanotubeBlocks and Systems Using Same and Methods of Making Same,” filedconcurrently herewith. Examples of contact and conductors materialsinclude elemental metals such as Al, Au, W, Ta, Cu, Mo, Pd, Ni, Ru, Ti,Cr, Ag, In, Ir, Pb, Sn, as well as metal alloys such as TiAu, TiCu,TiPd, PbIn, and TiW, other suitable conductors, or conductive nitridessuch as TiN, oxides, or silicides such as RuN, RuO, TiN, TaN, CoSi_(x)and TiSi_(x). Insulators may be SiO₂, SiN, Al₂O₃, or another insulatormaterial.

Laboratory ON/OFF switching test results of a nonvolatile nanotube blockswitch corresponding to NV NT block switch 5000 are described withrespect to graph 5070 illustrated in FIG. 5B, where write 0 correspondsto erase and results in a high resistance OFF state, and write 1corresponds to program and results in a low resistance ON state. Testconditions and results are described in more detail in the incorporatedpatent references. Graph 5070 illustrates results of electrical teststhat apply one write 0 voltage pulse of 6 volts, one write 1 voltagepulse of 6 V, and measure ON resistance at each ON/OFF cycle for 100cycles. ON resistance values 5075 are typically in the 120 kOhm to 1MOhm range and OFF resistance values 5080 are typically above 100 MOhmswith most values above 1 GOhm.

Insulators Applied to 2-D NV NT Switch and 3D NV NT Block SwitchStructures

Some embodiments of NV NT switches and NV NT block switches may beformed on the top surface of a chip and packaged in a hermeticallysealed environment without the use of insulators. Non-insulated NV NTswitches illustrated further above with respect to FIGS. 2A and 3 forexample are formed when nanotube elements are deposited and patterned ontop surfaces of co-planar contact terminals and insulators. Examples ofinsulated NV NT switches and NV NT block switches are described furtherbelow.

For chips with NV NT switches that are packaged in non-hermeticallysealed environments, then one or several insulator layers may be addedto the NV NT switch structure. Also, for denser memory cells forexample, NV NT switches may be integrated near a cell select transistorsuch as NFET, close to a silicon substrate and below bit line arrayswires for example. Therefore, multiple insulating layers may be usedabove NV NT switches integrated in some memory array structures.Insulators may interact with nanotube elements to change electricalproperties of NV NT switches such as voltage threshold and currentvalues required for switching. Some insulators may enhance electricalcharacteristics by lowering threshold voltages and currents. Examples ofNV NT switch insulator approaches are illustrated further below withrespect to FIGS. 5A, 6A-6D, 7A, 7B, and 8A-8C. In some cases, adding oneor more insulating layers may involve the use of one or more additionalmasking layers.

Some embodiments of NV NT block switches may be fabricated with a topcontact to a conductor such that insulators are not in contact with thetop surface of NV NT block structures as illustrated in FIGS. 1B and 1C,and FIGS. 4A and 5A. However, insulators may be in contact with somesidewall surfaces for NV NT block switch structures illustrated in FIGS.4A and 5A. NV NT block switches operate with a wide variety of contactconfigurations such as top and bottom and top/side and bottom contactsas illustrated in FIGS. 4A-4B and 5A-5B, as well as and other contactconfigurations such as end-only, end and side-contacts, and othercontact options illustrated further in the incorporated patentreferences.

Some embodiments of NV NT block switches may have contacts toconductors-only (no insulators) on five of six faces, leaving only asmall portion of a bottom NV NT block region in contact with anunderlying insulator by forming covered or enclosed (enrobed) NV NTblock switches as illustrated further below with respect to FIG. 8C.Such covered or enclosed NV NT block switches may integrate more easilyat various levels of assembly than NV NT switches and other(non-enclosed) NV NT block switches because of reduced sensitivity ofnanotube electrical characteristics to various insulators commonly usedin integrated circuit processes and structures. In other words, coveredor enclosed NV NT block switches may be compatible with a broader rangeof insulators used in integrated circuit manufacturing. However, in someembodiments, covered or enclosed NV NT block switches may be less dense(have a larger footprint) than NV NT block switch 5000 with top andbottom contacts as illustrated in FIG. 5A.

FIG. 6A illustrates insulated NV NT switch 6000 formed by the additionof insulator 6010 to NV NT switch 2000 illustrated in FIG. 2A. Patternednanotube element 2035 may be in contact with underlying insulator 2030and overlying insulator 6010. Preferred passivation layers as describedfurther below and in the incorporated patent references may be used asinsulators 6010 and 2030 in NV NT switch 6000.

Passivation layers may have some or all of the following properties.First, the passivation layer may form an effective moisture barrier,substantially preventing exposure of the nanotubes to water. Second, thepassivation film may not interfere with, and, preferably, enhance theswitching mechanism of the memory device. Third, the passivation filmmay be compatible with other insulators, conductors, and semiconductorswith respect to the preferred process flow used to form the integratedstructure.

Passivation layers may be formed from any appropriate material known inthe CMOS industry, including, but not limited to: SiO₂, SiN, Al₂O₃,polyimide, and other insulating materials such as PSG (Phosphosilicateglass) oxide, LTO (planarizing low temperature oxide) oxide, sputteredoxide or nitride, flowfill oxide, CVD (chemical vapor deposition) ofoxide and nitride, ALD (atomic layer deposition) oxides. PVDF(Polyvinylidene Fluoride) insulating material may also be used.Combinations of these insulators, or other suitable insulators, may alsobe used.

Insulators 6010 and 2030 may also be formed using preferred methods todeposit and pattern sacrificial polymer polypropylene carbonate (PPC)dissolved in one or more organic solvents such as NMP or cyclohexanoneavailable in the industry. A description of the properties ofpolypropylene carbonate may be found, for example, in referencedtechnical data available from the company Empower Materials, Inc. Othersacrificial polymers such as Unity™ sacrificial polymer and polyethylenecarbonate sacrificial polymer may also be used. Information about Unity™polymer is available from the supplier BFGoodrich, Cleveland, Ohio.Sacrificial polymer usage is further described in the incorporatedpatent references. These materials may also be used in conjunction withother materials, i.e., PPC or Unity™ polymers with insulators such asSiO₂ as illustrated further in the incorporated patent references.

FIG. 6B illustrates insulated NV NT switch 6020 formed by addinginsulator 6025 in contact with patterned nanotube element 2035 andinsulator 6030 in contact with insulator 6025, contact terminals 2010and 2015, and portions of insulator 2030 to NV NT switch 2000illustrated in FIG. 2A. Insulator 6025 may be formed by preferredmethods of applying sacrificial polymers such as PPC and Unity describedfurther above. Insulator 6030, may be formed by preferred methods ofapplying an insulator such as SiO₂ for example.

FIG. 6C illustrates insulated NV NT switch 6040 that corresponds to NVNT switch 6020. However, when forming NV NT switch 6040, insulator 6025used in NV NT switch 6020 may be formed using a sacrificial polymer suchas PPC or Unity described further above that can be evaporated throughan insulating layer. FIG. 6C illustrates NV NT switch 6040 afterevaporation of sacrificial polymer insulator 6025 through insulatinglayer 6050 (SiO₂ for example) to form gap region 6045 above patternednanotube element 2035 as described in greater detail in the incorporatedpatent references.

FIG. 6D illustrates insulated NV NT switch 6060 which corresponds to NVNT switch 6040. However, sacrificial insulators (not shown) have beenevaporated through insulator 6050 to create gap region 6065 abovepatterned nanotube element 2035 and gap region 6065′ below nanotubeelement 2035, embedded in insulator 6070 below patterned nanotubeelement 2035. Enhanced performance characteristics of NV NT switcheshaving patterned nanotube elements with gap regions are describedfurther in the incorporated patent references.

FIG. 7A illustrates insulated NV NT Switch 7000 with self alignedchannel length L_(SW-CH) formed by adding insulator 7010 to NV NT switch3000 illustrated in FIG. 3. Patterned nanotube element 3045 contactsunderlying contact terminals 3010 and 3015, contact terminal extension3040, and insulator 3035. Patterned nanotube element 3045 also contactsoverlying insulator 7010. Passivation layers are described further aboveand also further below and in the incorporated patent references.

FIG. 7B illustrates insulated NV NT switch 7050 which corresponds to NVNT switch 7000. However, a sacrificial insulator has been evaporatedthrough insulator 7065, SiO₂ for example, to form gap 7060 above aportion of patterned nanotube 3045 positioned above the L_(SW-CH) regionand extending above the patterned nanotube element 3045 on both sides ofthe L_(SW-CH) channel region. Examples of gap regions are describedfurther above with respect to FIGS. 6A-6D and in greater detail in theincorporated patent references.

FIG. 8A illustrates an insulated NV NT block switch 8000 which issimilar to non-insulated NV NT block switch 4000 illustrated furtherabove in FIG. 4A. Insulated NV NT block switch 8000 may be used insteadof NV NT switches illustrated in FIGS. 6A-6D and 7A and 7B in memorycells. NV NT block switch 8000 illustrated in FIG. 8A is formed bydepositing insulator 8010 on the surface of NV NT block switch 4000 suchthat insulator 8010 is in contact with conductor 4045, including thecontact 4040 region, exposed side surfaces such as side surface 4043 ofNV NT block 4035, and insulator 4030. Insulator 8010 is not in contactwith the top surface of NV NT block 4035 because contact 4040B iscovered by conductor 4045, and is also not in contact with one sidesurface of NV NT block 4035 because contact 4040A is covered byconductor 4045. Insulator 8010 material may be similar to insulator 6010material described further above with respect to FIG. 6A.

NV NT block switch 8020 illustrated in FIG. 8B is formed by includingsacrificial polymer regions (not shown) similar to sacrificial regionsdescribed further above with respect to FIGS. 6A-6D and 7A-7B prior toforming insulator 8030. Such sacrificial polymer regions may remain inthe insulator structure as illustrated in FIG. 6B further above, or maybe evaporated through an insulator such as insulator 8030 to form gapregions such as illustrated in FIGS. 6C and 6D. Gap region 8040 preventscontact between insulator 8030 and exposed side surface 4043 of NV NTblock 4035. Other NV NT block 4035 side surfaces (not visible in FIG.8B) may include gap regions that prevent side surface contact between NVNT block 4035 and insulator 8030. Gap regions and preferred methods offabrication are described further above with respect to FIGS. 6C, 6D,and 7B, and in the incorporated patent references.

NV NT block switches have been demonstrated to electrically operate(switch between ON and OFF states) in a wide variety of geometries andcontact configurations such as top and bottom and top/side and bottomcontacts as illustrated in FIGS. 4A and 5A, as well as other contactconfigurations such as end-only, end and side-contacts, and othercontact options, such as those illustrated in U.S. patent applicationSer. No. (TBA), entitled “Nonvolatile Nanotube Diodes and NonvolatileNanotube Blocks and Systems Using Same and Methods of Making Same,”filed concurrently herewith. For flexibility and ease of integrating NVNT block switch-type configurations at nearly any level of semiconductor(or other type of) process flow with exposure to various materials andprocesses, it may be desirable to integrate NV NT block switches in sucha way as to enhance conductor contacts and to reduce non-conductor(insulator) contacts to side/top/bottom surfaces (faces) of NV NT blocksregions. A covered or enclosed (e.g., enclosed by conductor contacts) NVNT block configuration enables covered or enclosed NV NT block switcheswith contacts to conductors-only (no insulators) on five of six NV NTblock surfaces (faces), leaving only a small portion of a bottom NV NTblock surface in contact with an underlying insulator as describedfurther below with respect to FIG. 8C and referred to as overlap lengthL_(OL).

FIG. 8C illustrates enclosed (enrobed) NV NT block switch 8050 crosssection, which includes bottom contact terminal 8065 in contact withinsulator and wiring layer 8055, which in turn is in contact withsubstrate 8060. The top surface of bottom contact terminal 8065 andinsulator 8070 are coplanar. Bottom contact terminal 8065 contacts NV NTblock 8075 at bottom contact 8067. NV NT block 8075 extends beyond thesurface of bottom contact 8067 by an overlap distance L_(OL) on allsides and is in contact with the top surface of insulator 8070. L_(OL)may be on the order of 5 to 100 nm, for example. L_(OL) may bedetermined by mask alignment or by self aligned techniques using knownpreferred sidewall spacer methods as described in prior art U.S. Pat.No. 4,256,514 combined with preferred methods such aschemical-mechanical polishing (CMP) techniques as described in prior artU.S. Pat. No. 4,944,836, as illustrated further above with respect toFIG. 3.

A conductor encloses NV NT block 8075 on the top surface and on all sidesurfaces thereby forming a top/side contact terminal 8080. Top portion8080A of top/side contact terminal 8080 forms top contact 8083 with thetop surface of NV NT block 8075. Preferred methods of fabrication mayuse top portion 8080A of top/side contact terminal 8080 as a maskinglayer when forming the sidewall surfaces of NV NT block 8075. Sidewallconductor regions 8080B-1, 8080B-2 of top/side contact terminal 8080,and other sidewall regions not visible in FIG. 8C, may be formed bypreferred methods to deposit a conformal conductor layer and thendirectionally etching as shown in prior art U.S. Pat. No. 4,256,514 toform sidewall conductor regions 8080B-1 and 8080B-2. Preferreddirectional etch methods remove the remaining portions of conductormaterial on the surface of insulator 8070. Sidewall conductor regions8080B-1 and 8080B-2 form sidewall contacts 8082-1 and 8082-2 to sidesurfaces of NV NT block 8075.

Preferred methods deposit insulator 8085. Next, preferred methods etchvia hole 8087 to the top portion 8080A of top/side contact terminal8080. Next, preferred methods deposit a conductor layer that fills viahole 8087. Then, preferred methods such as CMP described in theincorporated patent references planarize the surface forming conductor8090 in contact with the top surface 8080A of top/side contact terminal8080.

In some embodiments, enclosed NV NT block switch 8050 dimensions may belarger than the minimum dimension F by two-times the amount of theoverlap length L_(OL) (2 L_(OL)) and two-times the thickness of sidewallconductors regions 8080B-1 and 8080B-2. By way of example, if L_(OL) is5 to 50 nm and the sidewall conductor regions 8080B-1 and 8080B-2 are 5to 50 nm, for example, then in some embodiments the minimum dimensionsof enclosed NV NT block switch 8050 dimensions are F+20 nm in crosssection to F+200 nm in cross section.

Examples of contact and conductors materials include elemental metalssuch as Al, Au, W, Ta, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn,as well as metal alloys such as TiAu, TiCu, TiPd, PbIn, and TiW, othersuitable conductors, or conductive nitrides such as TiN, oxides, orsilicides such as RuN, RuO, TiN, TaN, CoSi_(x) and TiSi_(x). Insulatorsmay be SiO₂, SiN, Al₂O₃, or another insulator material.

Enclosed NV NT block switch 8050 may be combined with a selecttransistor such as an NFET to create memory cells as illustrated furtherbelow with respect to FIG. 19 for example.

FIG. 8D summarizes some embodiments of 2-D NV NT switches and 3-D NV NTblock switches described further above with respect to FIGS. 2A-8C thatmay be used as nonvolatile nanotube storage nodes in memory arrays asdescribed further below. Nonvolatile nanotube storage nodes numbered1-13 in FIG. 8D correspond to 2-D and/or 3-D switch structures andincludes a brief description, a switch number and corresponding Figurenumber, and integration level constraints, if any. Some embodiments ofnon-insulated switches may be limited to top-only placement, while someembodiments of insulated switches may be placed at any level ofintegration because the insulation protects the switches from subsequentprocess steps.

Memory Cells and Arrays of Same Using 3-D Nonvolatile Nanotube BlockSwitches as Storage Elements

Some embodiments of NV NT switches and NV NT block switches may beintegrated with NFET select transistors to form nonvolatile memory cellsand arrays of same. Such nanotube switches may be placed at or near atop surface region above already partially formed cells that includeNFET select devices connected to word lines (WLs) and bit lines (BLs)for ease of integration.

An exemplary 16 bit memory array was designed, fabricated and tested asdescribed further below with respect to FIGS. 9A, 9B, 10A, 10B, and11A-11C. Uninsulated NV NT block switches 4000 illustrated in FIG. 4Awere fabricated on a top layer of a CMOS chip with one terminalelectrically connected to sources of a corresponding with NFET selecttransistors to complete a nonvolatile 16 bit memory array with CMOSbuffer circuits as described further below.

Various memory array cells using NV NT switches and NV NT block switchesdescribed further above and summarized in FIG. 8D are described furtherbelow with respect to FIGS. 12A, 12B, 13A, 13B, 14A, 14B, and 15. Thesememory cells use NV NT storage nodes formed of NV NT switches and NV NTblock switches placed at or near a surface of the memory cell and abovepre-wired word and bit line layers.

Various memory array cells using NV NT switches and NV NT block switchesdescribed further above and summarized in FIG. 8D are described furtherbelow with respect to FIGS. 16A, 16B, 17A, 17B, 18A, 18B, and 19. Thesememory cells use NV NT storage nodes formed of NV NT switches and NV NTblock switches integrated within cells in close proximity to NFET selectdevices, with one terminal connected to the source of the NFETtransistor, and below the bit line layer to enhance cell density.

FIG. 20A illustrates a NV NT block switch storage node connected betweenbit line BL and NFET transistor drain. Such an integration scheme isenabled by the density of the NV NT block switches and the bidirectionalnature of current flow of the NV NT block switch.

FIG. 20B illustrates the cell areas (footprints) of various NV NTstorage nodes formed with NV NT switches or NV NT block switches. Cellareas are expressed in terms of the number of minimum squares ofdimension F×F. For NV NT storage nodes located at or near a surfaceabove pre-wired cell regions, cell areas depend on whether self-alignedor non-self aligned studs are used to contact the source of the NFETselect transistor with one terminal of the NV NT switch or NV NT blockswitch. In some embodiments, NV NT block switches with top and bottomcontacts (referred to as node # 10) and integrated within the cellregion, below the bit lines, have an estimated cell area in the range of6-8F².

16 bit Memory Array using NV NT Block Switches as Nonvolatile NanotubeStorage Nodes

Nonvolatile memory array schematic 9000 includes a matrix of 16nonvolatile storage cells C00, C10, . . . , C33 as illustrated in FIG.9A. Memory arrays are not limited to 16 cells and may have millions orbillions of cells for example. Each memory cell illustrated in memoryarray schematic 9000, such as representative cell C00, includes a selecttransistor T00 that may be an NFET as shown, or may also be a PFET (notshown) or a CMOS transfer device (not shown) that includes both NFET andPFET devices, or other types of switching devices (not shown). Eachcell, such as cell C00, also includes a nonvolatile nanotube storagenode NT00. Nonvolatile nanotube storage node NT00 (NV NT storage node)may be formed using NV NT switch-types and NV NT block switch-types suchas those illustrated further above and summarized in FIG. 8D.

Nonvolatile storage cells such as cell C00 are formed by connecting thesource SC00 of a transistor such as NFET T00 to a first terminal of a NVNT storage node such as NV NT storage node NT00 illustrated in FIG. 9A.Examples of NV NT storage nodes are listed in FIG. 8D.

Memory array schematic 9000 is formed by connecting word lines WL0, WL1,WL2, and WL3 to corresponding gates of NFET select transistors incorresponding storage cells; connecting secondary word lines WWL0, WWL1,WWL2, and WWL3 to corresponding second terminals of NV NT storage nodesin corresponding storage cells; and connecting bit lines BL0, BL1, BL2,and BL3 to corresponding drain diffusions of corresponding NFET selecttransistors in corresponding nonvolatile storage cells as illustrated inFIGS. 9A and 9B. For example, word line WL0 is connected to the gate ofNFET T00 by contact GC00; secondary word line WWL0 is connected to thesecond terminal of nonvolatile nanotube storage node NT00 by contactNC00; and bit line BL0 is connected to the drain of T00 by contact DC00.

Memory array layout 9002 illustrated in planar view in FIG. 9B is alayout (design) of an exemplary 16 bit memory array corresponding tomemory array schematic 9000 using 250 nm CMOS design rules. Selecteddesign workstation layout levels are highlighted.

Cells C00 and C10 of memory array layout 9002 illustrated in FIG. 9B areformed within the same FET region 9005 and share a common draindiffusion. Word line WL0 contacts the gate of the cell C00 select NFETtransistor at contact 9007, which corresponds to contact GC00 betweenword line WL0 and the gate of NFET T00 in memory array schematic 9000illustrated in FIG. 9A. Drain contact 9010 is shared by mirror-imagecells C00 and C10 illustrated in FIG. 9B, and contacts conductor segment9015 which in turn contacts bit line BL0 through contact 9020. Contact9010 illustrated in FIG. 9B corresponds to drain contacts DC00 of NFETT00 and DC10 of NFET T01 illustrated in FIG. 9A. A first contact tononvolatile nanotube storage node NT00 illustrated in FIG. 9A isconnected to the source of NFET T00 by contact SC00. NV NT block switch4000 illustrated in FIG. 4A (NV NT storage node number 9 in FIG. 8D) isplaced above the source of the cell C00 select NFET with NV NT block4035 bottom contact 4015 extended to contact the cell C00 NFET sourcediffusion as illustrated further below with respect to FIG. 13B.Combined upper/side contact 4040 to NV NT block 4035 is connected to(part of) conductor 4045 illustrated in FIG. 4A and corresponds toconductor segment 9030 in FIG. 9B. Conductor segment 9030 is alsoconnected to second word line WWL0 by contact 9035, which corresponds tocontact NC00 in FIG. 9A. All C10 NFET select devices and NV NT blockswitches are interconnected in a corresponding manner to those describedwith respect to cell C00. All other cells correspond to cell C00 or amirror image of cell C00 as described further above.

SEM image 10000 illustrated in FIG. 10A shows a plan view of partiallyfabricated memory cells just prior to the formation of NV NT blockswitches corresponding to NV NT block switch 4000 illustrated in FIG.4A, which are formed above underlying cell select transistors and arraywiring corresponding to memory array layout 9200. A blanket (porous)nanotube fabric layer of approximately 40 nm thick deposited usingpreferred methods covers the surface insulator and wiring layer 10200but is not visible in this SEM image due to insufficient contrast.However, a corresponding (porous) patterned nanotube block isillustrated further below by an SEM image in FIG. 10B. The blanketnanotube fabric layer was deposited using spray coating. However, ablanket nanotube fabric layer may also be formed by spin coatingmultiple individual nanotube fabric layers. Contact terminal 10100illustrated in FIG. 10A corresponds to contact terminal 4010 illustratedin FIG. 4A and contact terminal 10150 corresponds to contact terminal4015. The blanket nanotube fabric layer not visible in SEM image 10000is in contact with the top coplanar surfaces of contact terminals 10100and 10150 and with the top surface of insulator and wiring layer 10200,which corresponds to insulator and wiring layer 4030 in FIG. 4A.Patterned mask 10250 images on the surface of the blanket nanotubefabric layer and overlapping contact terminals 10150 are used to protectthe underlying portion of the blanket nanotube fabric layer from anoxygen plasma etch step later in the process flow. Patterned mask images10250 may be formed using Al₂O₃, or Ge, or any other compatible hardmask material.

Next, preferred methods etch the exposed portion of the blanket nanotubefabric layer in an oxygen plasma for example, as described further inthe incorporated patent references. Next, preferred methods removepatterned mask 10250 images. Then, preferred methods form conductorsegments 10400 shown in SEM image 10300 illustrated in FIG. 10Acorresponding to conductor segment 9030 illustrated in FIG. 9B andconductor 4045 illustrated in FIG. 4A. Conductor segment 10400 alsoforms a top/side contact to the underlying NV NT block (not visible)corresponding to contact 4040 illustrated in FIG. 4A. In this example,conductor segment 10400 is formed of Ti/Pd of thickness 2/100 nm,although other metals may be used. Then, preferred methods etchremaining exposed regions of nanotube fabric using conductor segment10400 as a mask layer to form NV NT block switches 10450 correspondingto NV NT block switch 4000 illustrated in FIG. 4A with conductor segment10400 corresponding to combined top/side contact 4040 and conductor4045, and bottom contact 10150 corresponding to bottom contact 4042,respectively.

At this point in the process, fabrication of the 16 bit memory arraycorresponding to 16 bit memory array layout 9002 is complete and SEMimage 10300 of FIG. 10A shows a plan view of top layers. The NV NT blockcorresponding to NV NT block 4035 in FIG. 4A is not visible in SEM image10300. However it is visible further below in FIG. 10B. Insulator andwiring layer 10200′ corresponds to insulator and wiring layer 10200 butwithout the blanket nanotube fabric layer.

SEM image 10500 illustrated in FIG. 10B illustrates an SEM tilt crosssection image. Contact terminal 10550 on the surface of insulator andwiring layer 10600 corresponds to contact terminal 10150 in SEM image10300 and forms a bottom contact to NV NT block 10650. Top contactterminal 10700 corresponds to that region of conductor segment 10400 inSEM image 10300 that forms a top contact to NV NT block 10650. NV NTblock 10650 is approximately 25×80 nm in this example.

Test and characterization of the 16 bit memory array 9000 illustrated inschematically in FIG. 9A, in layout form with NV NT block switch storagedevices illustrated in FIG. 9B, and in an SEM image 10300 of the NV NTblock switch storage region formed on top layers of the 16 bit memoryarray structure as illustrated in FIG. 10A, is carried out based onON/OFF state switching and resistance state readout. ON/OFF stateswitching results for NV NT block switches are illustrated by waveforms4500 in FIG. 4B for switching using a single pulse of approximately 6volts for transition between ON and OFF states. Write 0 operationsswitch NV NT block switches from ON to OFF or high resistance state andwrite 1 operations switch NV NT block switches from OFF to ON or lowresistance state. As illustrated in FIG. 4B, ON resistance values aretypically in the 100's of KOhm range, and OFF resistance values aretypically in the giga-Ohm range. If multiple pulses are used for write 0and write 1 operation, switching voltages may be lower than 6 volts forexample. Write 0, write 1, and read voltage and current waveforms may beas described in U.S. patent application Ser. No. 11/280,786 and U.S.Patent Application No. (TBA), entitled “Nonvolatile Nanotube Diodes andNonvolatile Nanotube Blocks and Systems Using Same and Methods of MakingSame,” filed concurrently herewith.

16 bit memory array 9000 illustrated schematically in FIG. 9A and inlayout in FIG. 9B has CMOS buffer circuits (not shown) between pads andword lines (WLs) and buffer circuits (not shown) between pads and bitlines (BLs) as fabricated. Second word lines (WWLs) are connecteddirectly to pads without CMOS buffer circuits.

In operation, at relatively low voltages such as 5 volts for example,write 0, write 1, and read operations may be performed by word and bitlines with secondary word lines at a reference voltage such as ground.For higher voltages, greater than 5 volts for example, write 0 and write1 pulses may be applied using secondary word lines with cells selectedby a corresponding word line, thereby reducing the voltage across cellselect transistors and CMOS buffer circuits. This ability to changeapplied voltage polarity and current direction is enabled by thebidirectional properties of NV NT block switches (also applies to NV NTswitches) that switch regardless of the applied voltage polarity andcurrent flow direction. As part of the 16 bit memory array 9000characterization, write 0 and write 1 voltages to individual cells werevaried over a wide range (schoomed) voltage values and therefore write 0and write 1 pulses were applied using secondary word lines. Readoperations used low voltage bit line discharge (typically less than 4volts for example) with word lines activated and secondary word linesgrounded.

Display readout 11000 illustrated in FIG. 11A shows the results of write0, write 1, and read operations on an exemplary 16 bit memory array 9000with NV NT block switches as described further above. For a write 0operation, all four bits along a selected word line are erasedsimultaneously. Hence, bit lines BL0, BL1, BL2, and BL3 are all held atzero volts and a selected word line such as word line WL0 is switchedfrom 0 volts to a higher voltage such as 5 volts for example. Then, oneor several voltage pulse/pulses is/are applied to correspondingsecondary word line WWL0. The WWL0 pulse amplitude may be varied from 4to 8 volts, for example. Corresponding NV NT block switch NT00 switchesfrom ON to OFF, or remains in the OFF state. Write 0 operations arerepeated with WL1 and WWL1, WL2 and WWL2, and WL3 and WWL3 until allbits are in on OFF state. Bit pattern 11100 illustrated in FIG. 11Arepresents a write 0 (OFF state) for each of the 16 bits in 16 bitmemory array 9000 such that each bit is an OFF or high resistance state.

For a read operation, a bit line such as bit line BL0 is switched to avoltage less than 3 or 4 volts, for example, and a selected word linesuch as word line WL0 activates an NFET select transistor such as T00 toan ON state and connects BL0 through a corresponding NV NT block such asNT00 to corresponding secondary word line such as WWL0 which isgrounded. If the corresponding NV NT block switch NT00 is in an OFFstate, BL0 remains unchanged and a “0” or OFF state is detected.However, if corresponding NV NT block switch NT00 is in a “1” or ONstate, then bit line BL0 voltage is reduced (droops) and a “1” state isdetected. In this example, a read operation results in bit pattern 11150where all bits are in a “0” or OFF state such that output bit pattern11150 corresponds to input bit pattern 11100.

A write 1 operation is performed one bit at a time along a selected wordline such as WL0 and corresponding secondary word line WWL0, forexample. A logic “1” or low resistance state is written in cell C00 byholding bit line BL0 at zero volts, while bit lines BL1, BL2, and BL3are held at a higher voltage such as 4 or 5 volts for example. Then, oneor several voltage pulse/pulses is/are applied to correspondingsecondary word line WWL0. The WWL0 pulse amplitude may be varied from 4to 8 volts, for example, and cell C00 switches from a logic “0” highresistance state and stores a nonvolatile logic “1” or low resistancestate on NT00. C01 is to store a zero in this example, therefore nopulses are applied since the entire array was erased prior to the write0 operation as described further above with respect to write 0operations.

The write 1 operation proceeds one bit at a time as described above withrespect to the write 1 operation description further above untilcheckerboard pattern 11200 is written in memory array 9000. In thisexample, checkerboard pattern 11200 is applied to the pre-erased 16 bitmemory array 9000. Then, a read operation results in a correspondingcheckerboard bit pattern 11250, and the 16 bits in memory array 9000remain stored in nonvolatile logic “0” or “1” state as illustrated bydisplay readout 11000.

Individual NV NT block switches 10450 illustrated in FIG. 10A areswitched between ON and OFF, low and high resistance statesrespectively, as a function of applied voltages as described furtherabove. In a first case, described further below with respect to FIG.11B, fast rise and fall times such as 2 ns are used. In a second case,described further below with respect to FIG. 11C, slow rise and falltimes such as 10 us are used. In both cases 10 pulses were used for bothwrite 0 and write 1 switching. Also, in both cases, hold time of 20 usfor write 0 and 1 ms for write 1 are used. Generally, test conditionsare similar to those described with respect to ON/OFF switchingdescribed with respect to FIGS. 4B and 5B and U.S. patent applicationSer. No. 11/280,786 and U.S. patent application Ser. No. (TBA), entitled“Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and SystemsUsing Same and Methods of Making Same,” filed concurrently herewith.

Schmoo plot 11400 illustrated in FIG. 11B shows pass and fail regionsfor write 0 operations in a range of 1 to 7 volts along the horizontalaxis and write 1 operations in a range of 1 to 7 volts in the verticaldirection. Pass region 11450 shows that write 0 and write 1 operationswith applied voltages of 4 volts and above result in successfulswitching of NV NT block switches similar to NV NT block switches 10450.Write 0 and write 1 voltages outside pass region 11450 are fails.

Schmoo plot 11500 illustrated in FIG. 11C shows pass and fail regionsfor write 0 operations in a range of 1 to 12 volts along the horizontalaxis and write 1 operations in a range of 1 to 12 volts in the verticaldirection. Pass region 11550 shows that write 0 and write 1 operationswith applied voltages of 4 volts and above result in successfulswitching of NV NT block switches similar to NV NT block switches 10450.Write 0 and write 1 voltages outside pass region 11550 are fails. Oneexception is a NV NT block switch that, in some embodiments, switches ata minimum of 5 volts for the write 1 operation as indicated by location11600.

Memory Arrays using NV NT Switches or NV NT Block Switches asNonvolatile Nanotube Storage Nodes with Bit Lines Adjacent to the NVStorage Node Location

Memory arrays may be formed by interconnecting nonvolatile memory cellsthat include a select transistor such as an NFET, a nonvolatile nanotubestorage node such as a NV NT switch or a NV NT block switch, andinterconnects within the cell and between the cell and array lines suchas word lines, bit lines, and secondary word lines as shown in memoryarray schematic 9000 illustrated in FIG. 9A. FIG. 8D summarizes varioustypes of nonvolatile nanotube storage nodes 1-13, includes a briefdescription of each type of NV NT storage node, integration level withinan integrated structure, and corresponding Figure numbers.

For ease of integration, some embodiments of nonvolatile nanotubestorage nodes such as NV NT switches or NV NT block switches may bepositioned at or near the top of the memory array structure, andoptionally offset relative to memory array bit lines further below inthe integrated structure, in order to facilitate a direct verticalconnection between a first nonvolatile nanotube storage node and anunderlying source of a corresponding NFET select transistor. That is,the NFET select transistor, stud connection to source and draindiffusions, and array lines such as word lines, bit lines, and secondarybit lines can be formed prior to the formation of the nonvolatilenanotube storage node, which can be formed at or near the end of theprocess flow. Nonvolatile nanotube storage nodes placed at or near thetop of integrated structures provide enhanced flexibility in theselection of contact terminal metals and insulator options, as well asno-insulator options, that may enhance the electrical performance of thenonvolatile nanotube storage node. In some embodiments, however, cellareas may be somewhat larger, e.g., 50% to 100% larger, and in someconfigurations, more than 200% larger.

Memory cells with NV NT switches or NV NT block switches at or near thetop of memory cells are described further below with respect to FIGS.12A-15 with cell area summarized in FIG. 20B, which is described furtherbelow.

Memory Arrays using NV NT Switches Placed Above the Array Wiring

FIG. 12A illustrates a plan view of memory array 12000 showing fourmemory cells that use NV NT switches as nonvolatile storage devices ator near the top of the memory array 12000 structure. FIG. 12Billustrates corresponding memory array 12000′ cross section taken alongsegment A1-A1′. Memory cells 12050A and 12050B are mirror images of oneanother. Memory cell 12050A will be used to describe the cell structuretypical of cells in memory array 12000. While memory cell 12050A showsNV NT storage node 12150A as non-insulated NV NT switch 2000 illustratedin FIG. 2A further above and listed in FIG. 8D as NV NT storage node #1,any of the insulated or non-insulated NV NT storage nodes numbered 1-8and listed in FIG. 8D may be used instead as NV NT storage node 12150A.

Cell select transistor 12100A includes source 12200 and drain 12250formed in silicon substrate 12300. Gate 12350, fabricated with sidewallspacers 12400, is part of array word line 12350 that forms gate regionsand array interconnections and controls channel region 12450 ON and OFFstates using well known FET device operating methods. Alternatively, aseparate word line conductor (not shown) may be used to interconnectgate regions of select devices such as cell select transistor 12100Aillustrated in FIGS. 12A and 12B. Stud 12500, embedded in dielectric12625, provides a conductive path between source 12200 and stud 12550,which in turn forms a first contact terminal of NV NT switch 12150A. Asecond contact terminal 12600 of NV NT switch 12150A is segment ofsecondary word line 12600. NV NT element 12650 contacts the top coplanarsurface of contact terminal 12550 and a segment of secondary word line12600 and also the top surface of coplanar insulator 12625. NV NT switch12150B is a mirror image of NV NT switch 12150A.

Drain 12250 of cell select transistor 12100A contacts stud 12700, whichin turn contacts conductor segment 12750 at contact 12800. Conductorsegment 12750 also contacts memory array bit line 12900 at contact 12850thereby connecting drain diffusion 12250 with bit line 12900. Drain12250 is shared with an adjacent cell (not visible in FIG. 12A or 12B).

As described further above, NV NT storage nodes 12150A and 12150B may beone of several non-insulated NV NT switches. For example, NV NT switch2000 illustrated in FIG. 2A and NV NT switch 3000 illustrated in FIG. 3may be used without a protective dielectric layer for applications wherechips are mounted in hermetic packages.

Alternatively, NV NT storage nodes 12150A and 12150B may be one ofseveral insulated NV NT switches. NV switches 6000 illustrated in FIG.6A, 6020 illustrated in FIG. 6B, 6040 illustrated in FIG. 6C, 6060illustrated in FIG. 6D, 7000 illustrated in FIG. 7A, and 7050illustrated in FIG. 7B may be used for example. Other embodiments canalso be used. These NV NT switches may be insulated with a singleinsulator layer, combinations of insulator layers, and combinations ofinsulator layers and gap regions as illustrated in the respectiveFigures described further above. Other embodiments cover the NV NTswitch with conductor, as described in greater detail herein.

In some embodiments, memory cells such as memory cells 12050A and 12050Bforming memory array 12000 are estimated to be approximately 20F² inarea, where F is a minimum technology node dimension. It is furtherassumed that self-aligned vertical studs are used when forming the cellstructure. Such stacked contacts and filled via holes (vertical studs)are illustrated in the prior art reference Ryan, J. G. et al., “Theevolution of interconnection technology at IBM”, Journal of Research andDevelopment, Vol. 39, No. 4, July 1995, pp. 371-381, the entire contentsof which are incorporated herein by reference. If vertical studs are notself-aligned, the cell area is estimated to grow by more than 2× in size(footprint), to greater than 40F² as illustrated in FIG. 20B, asdescribed in greater detail below.

Memory Arrays using NV NT Block Switches with Top/Side and BottomContacts Placed Above the Array Wiring

FIG. 13A illustrates a plan view of memory array 13000 showing fourmemory cells that use NV NT block switches as nonvolatile storagedevices at or near the top of the memory array 13000 structure. FIG. 13Billustrates corresponding memory array cross section 13000′ taken alongsegment A2-A2′. Memory cells 13050A and 13050B are mirror images of oneanother. Memory cell 13050A will be used to describe the cell structuretypical of cells in memory array 13000. While memory cell 13050A showsNV NT storage node 13150A as non-insulated NV NT block switch 4000illustrated in FIG. 4A further above and listed in FIG. 8D as NV NTstorage node #9, any of the insulated or non-insulated NV NT storagenodes numbered 9, 11, or 12 and listed in FIG. 8D may be used instead asNV NT storage node 13150A. NV NT block switch 4000 used to describememory array 13000 corresponds to NV NT block switch 10450 shown furtherabove in SEM image 10300 illustrated in FIG. 10A.

Cell select transistor 13100A includes source 13200 and drain 13250formed in silicon substrate 13300. Gate 13350, fabricated with sidewallspacers 13400, is part of array word line 13350 that forms gate regionsand array interconnections and controls channel region 13450 ON and OFFstates using well known FET device operating methods. Alternatively, aseparate word line conductor (not shown) may be used to interconnectgate regions of select devices such as cell select transistor 13100Aillustrated in FIGS. 13A and 13B. Stud 13500, embedded in dielectric13625, provides a conductive path between source 13200 and stud 13550,which in turn forms a first contact terminal to NV NT block 13650 of NVNT block switch 13150A. NV NT block 13650 overlaps both stud 13500 thatacts as a bottom contact terminal and a portion of the surface ofinsulator 13625, also referred further above as overlap length L_(OL). Asecond contact terminal to the top surface and one side surface of NV NTblock 13650 is formed by conductor segment 13675 that also contactsterminal 13600 of NV NT switch 13150A, which is a segment of secondaryword line 13600. NV NT block switch 13150B is a mirror image of NV NTblock switch 13150A.

Drain 13250 of cell select transistor 13100A contacts stud 13700, whichin turn contacts conductor segment 13750 at contact 13800. Conductorsegment 13750 also contacts memory array bit line 13900 at contact 13850thereby connecting drain diffusion 13250 with bit line 13900. Drain13250 is shared with an adjacent cell (not visible in FIG. 13).

As described further above, NV NT storage nodes 13150A and 13150B may bea non-insulated NV NT block switch. For example, NV NT block switch 4000illustrated in FIG. 4A may be used without a protective dielectric layerfor applications where chips are mounted in hermetic packages. 16 bitmemory array 9000 illustrated further above schematically in FIG. 9A, inlayout 9002 in FIG. 9B, and SEM image 10300 in FIG. 10A is an example ofa fabricated memory array 13000.

Alternatively, NV NT storage nodes 13150A and 13150B may be one ofseveral insulated NV NT block switches. NV block switches 8000illustrated in FIG. 8A and 8020 illustrated in FIG. 8B may be used forexample. These NV NT block switches may be insulated with a singleinsulator layer, combinations of insulator layers, and combinations ofinsulator layers and gap regions as illustrated in the respectiveFigures described further above.

In some embodiments, memory cells such as memory cells 13050A and 13050Bforming memory array 13000 are estimated to be approximately 20 F² inarea, where F is a minimum technology node dimension. It is furtherassumed that self-aligned vertical studs are used when forming the cellstructure. Such stacked contacts and filled via holes (vertical studs)are illustrated further in the incorporated references. If verticalstuds are not self-aligned, the cell area is estimated to grow by morethan 2× in size (footprint), to greater than 40F² as illustrated furtherbelow in FIG. 20B.

Memory Arrays using NV NT Block Switches with Top and Bottom ContactsPlaced Above the Array Wiring

FIG. 14A illustrates a plan view of memory array 14000 showing fourmemory cells that use NV NT block switches as nonvolatile storagedevices at or near the top of the memory array 14000 structure. FIG. 14Billustrates corresponding memory array cross section 14000′ taken alongsegment A3-A3′. Memory cells 14050A and 14050B are mirror images of oneanother. Memory cell 14050A will be used to describe the cell structuretypical of cells in NRAM memory array 14000. Memory cell 14050A usesinsulated NV NT block switch 5000 illustrated in FIG. 5A further aboveand listed in FIG. 8D as NV NT storage node #10.

Cell select transistor 14100A includes source 14200 and drain 14250formed in silicon substrate 14300. Gate 14350, fabricated with sidewallspacers 14400, is part of array word line 14350 that forms gate regionsand array interconnections and controls channel region 14450 ON and OFFstates using well known FET device operating methods. Alternatively, aseparate word line conductor (not shown) may be used to interconnectgate regions of select devices such as cell select transistor 14100Aillustrated in FIG. 14A and 14B. Stud 14500, embedded in dielectric14625, provides a conductive path between source 14200 and stud 14550,which in turn forms a first bottom contact terminal to NV NT block 14600of NV NT block switch 14150A. A second top contact terminal 14650 to NVNT block 14600 is used as a top contact terminal and may be used as amask when defining self-aligned NV NT block 14650 side surfaces asdescribed further in the incorporated patent references. Top contactterminal 14650 contacts secondary word line 14675. NV NT block switch14150B is a mirror image of NV NT block switch 14150A.

Drain 14250 of cell select transistor 14100A contacts stud 14700, whichin turn contacts conductor segment 14750 at contact 14800. Conductorsegment 14750 also contacts memory array bit line 14900 at contact 14850thereby connecting drain diffusion 14250 with bit line 14900. Drain14250 is shared with an adjacent cell (not visible in FIGS. 14A or 14B).

Memory cells such as memory cells 14050A and 14050B forming memory array14000 with NV NT block switches 14150A and 14150B as NV NT storage nodesform dense cells because of the compact 3-dimensional top and bottomcontact NV NT block switch geometry (structure). In some embodiments,memory cell area (footprint) is estimated to be approximately 12-15 F²in area, where F is a minimum technology node dimension. It is furtherassumed that self-aligned vertical studs are used when forming the cellstructure. Such stacked contacts and filled via holes (vertical studs)are illustrated further in the incorporated references. If verticalstuds are not self-aligned, the cell area is estimated in someembodiments to grow by more than 2× in size (footprint), to greater than30F² as illustrated in FIG. 20B, described in greater detail below.

Memory Arrays using Enclosed NV NT Block Switches with Top/All-Sides andBottom Contacts Placed Above the Array Wiring

FIG. 15 illustrates a cross section of memory array 15000 showing twomemory cells that use enclosed NV NT block switches as nonvolatilestorage devices at or near the top of the memory array 15000 structure.Memory cells 15050A and 15050B are mirror images of one another. Memorycell 15050A will be used to describe the cell structure typical of cellsin memory array 15000. Memory cell 15050A replaces insulated NV NT blockswitch 5000 used in memory cell 14050A and listed in FIG. 8D as NV NTstorage node #10 with insulated enclosed NV NT block switch 8050illustrated in FIG. 8C further above and listed in FIG. 8D as NV NTstorage node #13.

Insulators in contact with NV NT block surfaces may leave the electricalcharacteristics unchanged, may enhance the electrical characteristics,or may even limit the electrical operation of NV NT block switches. Inorder to facilitate NV NT block switch integration in memory arrays,sensitivity to choice of insulator material may be reduced or eliminatedby using an enclosed NV NT block switch that includes a top/all-sidescontact terminal which prevents top and all-side surface contacts of thecorresponding NV NT block with insulators. Memory cell 15050A is similarto cell 14050A illustrated in FIGS. 14A and 14B in plan view (layout)and cross section, respectively. Therefore, only a cross section ofmemory array 15000 is shown in FIG. 15. Enclosed NV NT block switch15150A is a modification of NV NT block switch 14150A in which aconductor in contact with the top surface of NV NT block 15600 alsoencloses (enrobes) NV NT block 15600 to create top/all-sides contacts asdescribed further above with respect to enclosed NV NT block switch 8050shown in FIG. 8C. The enveloping (enrobing) conductor may be relativelythin, 5 to 50 nm for example, and is used to form enclosed NV NT blockside surface contacts and prevent side surface contacts with insulatormaterial.

Cell select transistor 15100A includes source 15200 and drain 15250formed in silicon substrate 15300. Gate 15350, fabricated with sidewallspacers 15400, is part of array word line 15350 that forms gate regionsand array interconnections and controls channel region 15450 ON and OFFstates using well known FET device operating methods. Alternatively, aseparate word line conductor (not shown) may be used to interconnectgate regions of select devices such as cell select transistor 15100Aillustrated in FIG. 15. Stud 15500, embedded in dielectric 15625,provides a conductive path between source 15200 and stud 15550, which inturn forms a first bottom contact terminal to NV NT block 15600 ofenclosed NV NT block switch 15150A. A top/all-sides contact terminal15650 in contact with the top surface and all side surfaces of NV NTblock 15600 forms a second contact and is also in contact with secondaryword line 15675 as shown in cross section in FIG. 15. NV NT block switch15150B is a mirror image of NV NT block switch 15150A.

Drain 15250 of cell select transistor 15100A contacts stud 15700, whichin turn contacts conductor segment 15750 at contact 15800. Conductorsegment 15750 also contacts a memory array bit line (not shown in FIG.15) but corresponding to memory array bit line 14900 in FIG. 14A at acontact (not shown) corresponding to contact 14850 in FIG. 14A therebyconnecting drain diffusion 15250 with a bit line (not shown)corresponding to bit line 14900 in FIG. 14A. Drain 15250 is shared withan adjacent cell (not visible in FIG. 15).

Memory cells such as memory cells 15050A and 15050B forming memory array15000 with enclosed NV NT block switches 15150A and 15150B as NV NTstorage nodes form cells that may be less dense than cells 14150A and14150B because of top/all-sides contact terminal 15650 lateral thicknessand the separation (L_(OL) as referred to further above) between theedges of bottom contact terminal 15550 and top/all-sides contactterminal 15650, but may be denser than cells 13150A and 13150B forexample. In some embodiments, memory cell area (footprint) is estimatedto be approximately in the range of 15-20F² in area, where F is aminimum technology node dimension. It is further assumed thatself-aligned vertical studs are used when forming the cell structure.Such stacked contacts and filled via holes (vertical studs) areillustrated further in the incorporated references. If vertical studsare not self-aligned, in some embodiments the cell area is estimated togrow by more than 2× in size (footprint), to greater than 30-40F² asillustrated in FIG. 20B, described in greater detail below.

Memory Arrays using NV NT Switches or NV NT Block Switches asNonvolatile Nanotube Storage Nodes with NV Storage Node Integrated toEnhance Cell/Array Density (Reduce Cell/Array Footprint)

In some embodiments, memory arrays are formed by interconnectingnonvolatile memory cells that include a select transistor such as anNFET, a nonvolatile nanotube storage node such as a NV NT switch or a NVNT block switch, and interconnect means within the cell and interconnectmeans between the cell and array lines such as word lines, bit lines,and secondary word lines as shown in memory array schematic 9000illustrated in FIG. 9A. FIG. 8D summarizes various types of nonvolatilenanotube storage nodes 1-13, includes a brief description of each typeof NV NT storage node, integration level within an integrated structure,and corresponding Figure numbers.

In order to enhance cell/array density (reduce cell/array footprint),nonvolatile nanotube storage nodes such as NV NT switches or NV NT blockswitches may be embedded in memory cells above the source of the selectNFET transistor and below array bit lines in the integrated structure,such that array bit lines may be positioned above select NFETtransistors in order to enhance cell density as illustrated furtherbelow with respect to FIGS. 16A-20A and summarized in FIG. 20B furtherbelow.

Memory Arrays using NV NT Switches Placed Below Array Bit Lines, Nearthe Select Transistor, and in Contact with the Source

FIG. 16A illustrates a plan view of memory array 16000 showing fourmemory cells that use NV NT switches as nonvolatile storage devicesembedded in memory array 16000 structure for enhanced cell/arraydensity. FIG. 16B illustrates corresponding memory array 16000′ crosssection taken along segment A4-A4′. Memory cells 16050A and 16050B aremirror images of one another. Representative memory cell 16050A will beused to describe the cell structure typical of cells in memory array16000. While memory cell 16050A shows NV NT storage node 16150A asinsulated NV NT switch 6000 illustrated in FIG. 6A further above andlisted in FIG. 8D as NV NT storage node #3, any of the insulated NV NTstorage nodes numbered 3-8 and listed in FIG. 8D may be used instead asNV NT storage node 16150A. Other embodiments can also be used.

Cell select transistor 16100A includes source 16200 and drain 16250formed in silicon substrate 16300. Gate 16350, fabricated with sidewallspacers 16400, is part of array word line 16350 that forms gate regionsand array interconnections and controls channel region 16450 ON and OFFstates using well known FET device operating methods. Alternatively, aseparate word line conductor (not shown) may be used to interconnectgate regions of select devices such as cell select transistor 16100Aillustrated in FIG. 16A and 16B. Stud 16500, embedded in dielectric16625, provides a conductive path between source 16200 and a firstcontact terminal of NV NT switch 16150A also embedded in dielectric16625, in which stud 16500 may be used as the first contact terminal ofNV NT switch 16150A. A second contact terminal 16600 of NV NT switch16150A is part of secondary word line 16600. NV NT element 16650contacts the top coplanar surface of contact terminals 16500. NV NTswitch 16150B is a mirror image of NV NT switch 16150A.

Drain 16250 of cell select transistor 16100A contacts stud 16700, whichin turn contacts stud 16900′ at contact 16800. Stud 16900′ is in contactwith bit line 16900 thereby interconnecting bit line 16900 and drain16250. Stud 16900′ and bit line 16900 may be formed at the same timeusing preferred methods of fabrication, such as the conductor depositionand chem.-mech polishing (CMP) methods described in U.S. Pat. No.4,944,836. Drain 16250 is shared with an adjacent cell (not visible inFIGS. 16A or 16B).

As described further above, NV NT storage nodes 16150A and 16150B may beone of several insulated NV NT switches. NV switches 6000 illustrated inFIG. 6A, 6020 illustrated in FIG. 6B, 6040 illustrated in FIG. 6C, 6060illustrated in FIG. 6D, 7000 illustrated in FIG. 7A, and 7050illustrated in FIG. 7B may be used for example. These NV NT switches maybe insulated with a single insulator layer, combinations of insulatorlayers, or combinations of insulator layers and gap regions asillustrated in the respective Figures described further above.

The plan view of memory array 16000 illustrated in FIG. 16A and thecorresponding cross section 16000′ illustrated in FIG. 16B show theintegrated structure fabricated through the bit line 16900 definitionlevel. Additional insulating (and conductor) layers may be formed abovebit line 16900 (not shown) including final chip passivation and chipterminal metal layers (not shown).

In some embodiments, memory cells such as memory cells 16050A and 16050Bforming memory array 16000 are estimated to be approximately 12-15F² inarea as illustrated further below in FIG. 20B, where F is a minimumtechnology dimension.

Memory Arrays using NV NT Block Switches with Top/Side and BottomContacts Placed Below Array Bit Lines, Near the Select Transistor, andin Contact with the Source

FIG. 17A illustrates a plan view of memory array 17000 showing fourmemory cells that use NV NT block switches with top/side and bottomcontact terminals as nonvolatile storage devices embedded in memoryarray 17000 structure for enhanced cell/array density. FIG. 17Billustrates corresponding memory array 17000′ cross section taken alongsegment A5-A5′. Memory cells 17050A and 17050B are mirror images of oneanother. Representative memory cell 17050A will be used to describe thecell structure typical of cells in memory array 17000. While memory cell17050A shows NV NT storage node 17150A as insulated NV NT block switch8000 with top/side and bottom contact terminals illustrated in FIG. 8Afurther above and listed in FIG. 8D as NV NT storage node #11, insulatedNV NT storage node 12 listed in FIG. 8D, or other insulatorconfigurations (not shown), may be used instead as NV NT storage node17150A.

Cell select transistor 17100A includes source 17200 and drain 17250formed in silicon substrate 17300. Gate 17350, fabricated with sidewallspacers 17400, is part of array word line 17350 that forms gate regionsand array interconnections and controls channel region 17450 ON and OFFstates using well known FET device operating methods. Alternatively, aseparate word line conductor (not shown) may be used to interconnectgate regions of select devices such as cell select transistor 17100Aillustrated in FIGS. 17A and 17B. Stud 17500, embedded in dielectric17625, provides a conductive path between source 17200 and a firstcontact terminal of NV NT block switch 17150A also embedded indielectric 17625, in which stud 17500 may be used as the first contactterminal to NV NT block 17650 of NV NT block switch 17150A. A secondcontact terminal 17675 of NV NT switch 17150A is formed by conductorsegment 17675 and forms top/side contacts to NV NT block 17650 andcontacts secondary word line 17600. NV NT switch 17150B is a mirrorimage of NV NT switch 17150A.

Drain 17250 of cell select transistor 17100A contacts stud 17700, whichin turn contacts stud 17900′ at contact 17800. Stud 17900′ is in contactwith bit line 17900 thereby interconnecting bit line 17900 and drain17250. Stud 17900′ and bit line 17900 may be formed at the same time asdescribed further above with respect to FIG. 16A-16B and in theincorporated patent references. Drain 17250 is shared with an adjacentcell (not visible in FIG. 17A or 17B).

As described further above, NV NT storage nodes 17150A and 17150B may beone of several insulated NV NT block switches such as NV NT block switch8000 illustrated in FIG. 8A and NV NT block switch 8020 illustrated inFIG. 8B for example. These NV NT block switches may be insulated with asingle insulator layer, combinations of insulator layers, andcombinations of insulator layers and gap regions as illustrated in therespective Figures described further above.

The plan view of memory array 17000 illustrated in FIG. 17A and thecorresponding cross section 17000′ illustrated in FIG. 17B show theintegrated structure fabricated through the bit line 17900 definitionlevel. Additional insulating (and conductor) layers may be formed abovebit line 17900 (not shown) including final chip passivation and chipterminal metal layers (not shown).

In some embodiments, memory cells such as memory cells 17050A and 17050Bforming NRAM memory array 17000 are estimated to be approximately12-15F² in area as illustrated further below in FIG. 20B, where F is aminimum technology node dimension.

Memory Arrays using NV NT Block Switches with Top and Bottom ContactsPlaced Below Array Bit Lines, Near the Select Transistor, and in Contactwith the Source

FIG. 18A illustrates a plan view of memory array 18000 showing fourmemory cells that use NV NT block switches with top and bottom contactterminals as nonvolatile storage devices embedded in memory array 18000structure for enhanced cell/array density. FIG. 18B illustratescorresponding memory array 18000′ cross section taken along segmentA6-A6′. Memory cells 18050A and 18050B are mirror images of one another.Representative memory cell 18050A will be used to describe the cellstructure typical of cells in memory array 18000. Memory cell 18050Ashows NV NT storage node 18150A as insulated NV NT block switch 5000with top and bottom contact terminals illustrated in FIG. 5A furtherabove and listed in FIG. 8D as NV NT storage node #10.

Cell select transistor 18100A includes source 18200 and drain 18250formed in silicon substrate 18300. Gate 18350, fabricated with sidewallspacers 18400, is part of array word line 18350 that forms gate regionsand array interconnections and controls channel region 18450 ON and OFFstates using well known FET device operating methods. Alternatively, aseparate word line conductor (not shown) may be used to interconnectgate regions of select devices such as cell select transistor 18100Aillustrated in FIGS. 18A and 18B. Stud 18500, embedded in dielectric18625, provides a conductive path between source 18200 and a firstcontact terminal of NV NT block switch 18150A also embedded indielectric 18625, in which stud 18500 may be used as a bottom contactterminal to NV NT block 18600 of NV NT block switch 18150A. A topcontact terminal 18650 in contact with the top surface of NV NT block18600 forms a second contact and is also in contact with secondary wordline 18675. NV NT block switch 18150B is a mirror image of NV NT switchblock 18150A.

Drain 18250 of cell select transistor 18100A contacts stud 18700, whichin turn contacts stud 18900′ at contact 18800. Stud 18900′ is in contactwith bit line 18900 thereby interconnecting bit line 18900 and drain18250. Stud 18900′ and bit line 18900 may be formed at the same time asdescribed further above with respect to FIGS. 16A-16B and 17A-17B and inthe incorporated patent references. Drain 18250 is shared with anadjacent cell (not visible in FIG. 18A or 18B).

As described further above, NV NT storage nodes 18150A and 18150B use NVNT block switches 5000 illustrated further above in FIG. 5A to enhancecell/array density (reduce cell/array footprint). While NV NT storagenodes 18150A and 18150B illustrate NV NT block switches 5000 insulatedwith a single insulator layer, combinations of insulator layers, andcombinations of insulator layers and gap regions as illustrated in therespective Figures described further above may also be used.

The plan view of memory array 18000 illustrated in FIG. 18A and thecorresponding cross section 18000′ illustrated in FIG. 18B show theintegrated structure fabricated through the bit line 18900 definitionlevel. Additional insulating (and conductor) layers may be formed abovebit line 18900 (not shown) including final chip passivation and chipterminal metal layers (not shown).

In some embodiments, memory cells such as memory cells 18050A and 18050Bforming NRAM memory array 18000 are estimated to be approximately 6-8F²in area as illustrated further below in FIG. 20B, where F is a minimumtechnology node dimension.

Memory Arrays using Enclosed (Enrobed) NV NT Block Switches withTop/All-Sides and Bottom Contacts Placed Below Array Bit Lines, Near theSelect Transistor, and in Contact with the Source

FIG. 19 illustrates a cross section of memory array 19000 showing twocells that use enclosed (enrobed) NV NT block switches as nonvolatilestorage devices placed below the bit lines and near the selecttransistors of memory array 19000 structure. Memory cells 19050A and19050B are mirror images of one another. Memory cell 19050A will be usedto describe the cell structure typical of cells in memory array 19000.Memory cell 19050A replaces insulated NV NT block switch 5000 used incell 18050A and listed in FIG. 8D as NV NT storage node #10 withinsulated enclosed NV NT block switch 8050 illustrated in FIG. 8Cfurther above and listed in FIG. 8D as NV NT storage node #13.

As mentioned above, insulators in contact with NV NT block surfaces mayleave the electrical characteristics unchanged, may enhance electricalcharacteristics, or may even limit the electrical operation of NV NTblock switches. In order to facilitate NV NT block switch integration inmemory arrays, sensitivity to choice of insulator material may bereduced or eliminated by using an enclosed NV NT block switch thatincludes a top/all-sides contact terminal that prevents top and all-sidesurface contacts of the corresponding NV NT block with insulators.Memory cell 19050A is similar to cell 18050A illustrated in FIGS. 18Aand 18B in plan view (layout) and cross section, respectively.Therefore, only a cross section of memory array 19000 is shown in FIG.19. Enclosed NV NT block switch 19150A is a modification of NV NT blockswitch 18150A in which a conductor in contact with the top surface of NVNT block 19600 also encloses (enrobes) NV NT block 19600 to createtop/all-sides contacts as described further above with respect toenclosed NV NT block switch 8050 shown in FIG. 8C. The enveloping(enrobing) conductor may be relatively thin, 5 to 50 nm for example, andis used to form enclosed NV NT block side surface contacts andsubstantially prevent side surface contacts with insulator material.

Cell select transistor 19100A includes source 19200 and drain 19250formed in silicon substrate 19300. Gate 19350, fabricated with sidewallspacers 19400, is part of array word line 19350 that forms gate regionsand array interconnections and controls channel region 19450 ON and OFFstates using well known FET device operating methods. Alternatively, aseparate word line conductor (not shown) may be used to interconnectgate regions of select devices such as cell select transistor 19100Aillustrated in FIG. 19. Stud 19500, embedded in dielectric 19625,provides a conductive path between source 19200 and a first contactterminal of NV NT block switch 19150A also embedded in dielectric 19625,in which stud 19500 may be used as a bottom contact to NV NT block 19600of NV NT block switch 19150A. A top/all-sides contact terminal 19650 incontact with the top surface and all-side surfaces of NV NT block 19600forms a second contact and is also in contact with secondary word line19675. NV NT block switch 19150B is a mirror image of NV NT block switch19150A.

Drain 19250 of cell select transistor 19100A contacts stud 19700, whichin turn contacts stud 19900′ at contact 19800. Stud 19900′ is in contactwith bit line 19900 thereby interconnecting bit line 19900 and drain19250. Stud 19900′ and bit line 19900 may be formed at the same time asdescribed further above with respect to FIGS. 16A-16B, 17A-17 B, and 18A-18B and in the incorporated patent references. Drain 19250 is sharedwith an adjacent cell (not visible in FIG. 19).

Memory cells such as memory cells 19050A and 19050B forming memory array19000 with enclosed NV NT block switches 19150A and 19150B as NV NTstorage nodes form cells that may in some embodiments be less dense thancells 18150A and 18150B because of top/all-sides contact terminal 19650lateral thickness and the separation (L_(OL) as referred to furtherabove) between the edges of bottom contact terminal 19500 andtop/all-sides contact terminal 19650, but may be denser than cells16150A and 16150B for example. In some embodiments, memory cell area(footprint) is estimated to be approximately in the range of 12-15F² inarea as illustrated further below in FIG. 20B, where F is a minimumtechnology node dimension.

Memory Arrays using NV NT Block Switches with Top and Bottom ContactsPlaced Below Array Bit Lines, Near the Select Transistor, with Bit LineContact to the Top Contact and Drain Contact to the Bottom Contact ofthe Switch

FIG. 20A illustrates a cross section of memory array 20000 that uses analternative placement of NV NT block switch 5000 illustrated in FIG. 5Abetween a bit line contact and a corresponding drain diffusion. Acorresponding secondary word line is connected to a corresponding sourceof the select NFET device. In some embodiments, the memory array density(footprint) of memory array 20000 is approximately equal to the memoryarray density (footprint) of memory array 18000 described further abovewith respect to FIGS. 18A-18B.

FIG. 20A illustrates a cross section of memory array 20000 showingmemory cells that use NV NT block switches with top and bottom contactterminals as nonvolatile storage devices embedded in memory array 20000structure for enhanced cell/array density. Memory cells 20050A and20050B are mirror images of one another. Representative memory cell20050A will be used to describe the cell structure typical of all cellsin memory array 20000. Memory cell 20050A shows NV NT storage node20150A as insulated NV NT block switch 5000 with top and bottom contactterminals illustrated in FIG. 5A further above and listed in FIG. 8D asNV NT storage node #10.

Cell select transistor 20100A includes source 20200 and drain 20250formed in silicon substrate 20300. Gate 20350, fabricated with sidewallspacers 20400, is part of array word line 20350 that forms gate regionsand array interconnections and controls channel region 20450 ON and OFFstates using well known FET device operating methods. Alternatively, aseparate word line conductor (not shown) may be used to interconnectgate regions of select devices such as cell select transistor 20100Aillustrated in FIG. 20A. Stud 20500, embedded in dielectric 20625,provides a conductive path between drain 20250 and a first contactterminal of NV NT block switch 20150A also embedded in dielectric 20625,in which stud 20500 may be used as a bottom contact terminal to NV NTblock 20600 of NV NT block switch 20150A. A top contact terminal 20650in contact with the top surface of NV NT block 20600 forms a secondcontact and is also in contact with stud 20900′. Stud 20900′ is incontact with bit line 20900 thereby interconnecting bit line 20900 andtop contact terminal 20650 of NV NT block switch 20150A. Stud 20900′ andbit line 20900 may be formed at the same time as described further abovewith respect to FIGS. 16A-16B, 17A-17B, 18A-18B, and 19 and in theincorporated patent references. NV NT switch 20150B is a mirror image ofNV NT switch 20150A.

Source 20200 of cell select transistor 20100A contacts stud 20700, whichin turn contacts secondary word line 20675 at contact 20800. Source20200 is shared with an adjacent cell (not visible in FIG. 20A).

As described further above, NV NT storage nodes 20150A and 20150B use NVNT block switches 5000 illustrated further above in FIG. 5A to enhancecell/array density (reduce cell/array footprint). While NV NT storagenodes 20150A and 20150B illustrate NV NT block switches 5000 insulatedwith a single insulator layer, combinations of insulator layers, andcombinations of insulator layers and gap regions as illustrated in therespective Figures described further above may also be used.

The cross sectional view of memory array 20000 illustrated in FIG. 20Ashows the integrated structure fabricated through the bit line 20900definition level. Additional insulating (and conductor) layers may beformed above bit line 20900 (not shown) including final chip passivationand chip terminal metal layers (not shown).

In some embodiments, memory cells such as memory cells 20050A and 20050Bforming memory array 20000 are estimated to be approximately 6-8F² inarea, where F is a minimum technology node dimension.

Note that while NV NT block switch 5000 illustrated in FIG. 5A is usedas NV NT block switch 20150A and 20150B, enclosed NV NT block switch8050 illustrated in FIG. 8C may be used instead if reduced contact withinsulator 20625 is desired. In such a case, the array area (footprint)may increase in size for the same reasons as described further abovewith respect to memory array 19000 illustrated in FIG. 19.

Summary of the Relative Memory Array Density (Footprint) of VariousEmbodiments of NV NT Switches, NV NT Block Switches, and Enclosed NV NTBlock Switches used as Nonvolatile Nanotube Storage Nodes

FIG. 20B summarizes cell sizes for some of the exemplary embodiments ofmemory arrays described further above based on the type and placement ofNV NT storage nodes. FIG. 20B also includes corresponding FIG. 8D NV NTstorage node numbers for ease of reference with the types of NV NTswitches, NV NT block switches, or enclosed NV NT block switches used asNV storage nodes in the various memory arrays.

NV NT storage nodes located at or near the top surface of arrays aboveword lines (WLs) and bit lines (BLs) that are already connected withNFET select transistors results in less dense implementations. However,NV NT storage nodes located at or near the surface of pre-wired memoryarrays offer ease of integration (integration flexibility) includingun-insulated chips for mounting in hermetic packages as well as NV NTstorage nodes insulated using a wide variety of insulator combinationsand gap regions. Such placement results in a short development time forNV NT switches and NV NT block switches integrated with CMOS circuitsand NFET select transistors. Cell area (footprint) may be substantiallylarger than for fully integrated structures as shown in FIG. 20B,however working memory arrays such as 16 bit memory array 9000 describedfurther above with respect to FIGS. 9A-9B, 10A-10B, and 11A-11C mayresult in faster memory array fabrication and accelerated learning. Notethat cell density (footprint) also depends on whether self aligned ornon-self aligned studs are used when connecting NV NT storage nodes toselect transistor source diffusions.

Fully integrated NV NT storage nodes placed below bit lines result inenhanced cell density (relatively small footprint). FIG. 20B showsvarious relative cell areas in terms of minimum dimension F. Someembodiments of relatively dense memory cells have an estimated cell areain the range of 6-8 F², which can be achieved by fully integrating a NVNT block switch with top and bottom contacts as shown in FIG. 20B. Foran F=45 nm technology node, cell area is estimated to be in the range of0.012-0.016 um²; for an F=22 nm technology node, cell area is estimatedto be in the range of 0.003-004 um²; and for an F=10 nm technology node,cell area is estimated to be in the range of 0.0006 to 0.0008 um². NV NTblock switches are scalable and dimensions in 22 to 45 nm range havebeen fabricated. There are no known fundamental barriers to scaling toan F=10 nm technology node, or even smaller.

Relatively Dense Cross Point Switches

Nonvolatile cross point switch matrices may be used to changeinterconnections in chips after fabrication is complete. NV NT blockswitches may be used to form relatively dense nonvolatile cross pointswitches for use in reconfigurable logic such as FPGAs for example.Dense nonvolatile cross point switches using NV NT block switches aredescribed further below with respect to FIGS. 20A-23C.

First-Type of Dense Cross Point Switch Structures with NV NT BlockSwitches Self Aligned to Array Wiring

Nonvolatile nanotube two terminal cross point switches based on a“picture frame” layout and using horizontally-oriented thin nanotubeelements are illustrated in FIG. 21 and correspond to two terminal crosspoint switches described in U.S. patent application Ser. No. 11/280,786.While the “picture frame” embodiment illustrated in FIG. 21 isrelatively dense (i.e., many can be fabricated in a small area; have asmall footprint), even denser scalable nonvolatile nanotube two terminalswitches may be made. Replacing horizontally-oriented (2-D) thinnanotube elements with vertically-oriented (3-D) two terminalnonvolatile nanotube block (NV NT Block) switches, such as thosedescribed further above and in U.S. patent application Ser. No. (TBA),entitled “Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocksand Systems Using Same and Methods of Making Same,” filed concurrentlyherewith, may result in still denser switches that are useful in manyapplications such as electronically programmable wiring, nonvolatilememory, logic including array logic, FPGAs, and other applications forexample.

FIG. 21 illustrates a picture frame two terminal nonvolatile nanotubeswitch 21000 cross section including a supporting insulator 21100 on anunderlying substrate (not shown) and conductive element 21105 in viahole 21110. Nonvolatile nanotube switch 21000 may be switched between ONand OFF states multiple times. Nanotube element 21125 is in contact withconductive element 21050 that forms one of the two nanotube switch 21000terminals. An optional conductive element 21107 may be used to enhancethe contact between nanotube element 21125 and conductive element 21105.Conductive element 21155 contacts the periphery of nanotube element21125 in region 21135 thereby forming a second two terminal nanotubeswitch 21000 terminal. Conductive element 21155 is separated fromoptional conductive element 21107 and portions of nanotube element 21125by insulator 21120. In some embodiments, two terminal nanotube switch21000 dimensions are approximately 3F in the horizontal X direction, and3F in the approximately orthogonal Y direction (not shown), where F isthe minimum lithographically defined dimension at a particulartechnology node. The minimum separation between adjacent switches is Fsuch that two terminal nanotube switches 21000 may be placed on aperiodicity (not shown) of 4F in the X and Y directions. In someembodiments, an individual two terminal nanotube switch 21000 occupiesan area of 9F², and 16F² when placed in an array configuration separatedfrom other switches by minimum distance F.

FIG. 22A illustrates a plan view of nonvolatile nanotube block switchmatrix 22000 of four vertically-oriented (3-D) two terminal nonvolatilenanotube block switches (22100-1, 22100-2, 22100-3, and 22100-4) in atwo-by-two cross point switch array configuration. Representative crosssections X1-X1′ and Y1-Y1′ through a portion of NV NT block switch22100-1 as illustrated in FIG. 22A further illustrate elements of NV NTblock switches in vertically-oriented (3-D) structures as shown in FIGS.22B and 22C. Details of first-type two terminal NV NT block switches andmethods of fabrication, corresponding to two-terminal nonvolatilenanotube switches 22100-1, 22100-2, 22100-3, and 22100-4 are describedfurther above and in the incorporated patent references. NV NT blocksmay be deposited using multiple spin-on layers or by spray on techniquesas described in the incorporated patent references, e.g., U.S. patentapplication Ser. No. (TBA), entitled “Nonvolatile Nanotube Diodes andNonvolatile Nanotube Blocks and Systems Using Same and Methods of MakingSame,” filed concurrently herewith.

Wire 22050-1 illustrated in FIG. 22A interconnects two terminal NV NTblock switches 22100-1 and 22100-2, forming bottom (lower level)contacts with each of these two terminal NV NT block switches havingdimensions F×F and separated by a distance F. Wire 22050-2 interconnectstwo terminal NV NT block switches 22100-3 and 22100-4, forming bottom(lower level) contacts, with each of these two terminal NV NT blockswitches having dimensions F×F and separated by a distance F.

While F represents minimum feature size to achieve maximum switch arraydensity, dimensions larger than F may be used as needed and non-squarecross sections may be used, such as rectangular and circular for examplein order to achieve lower ON resistance values or other desiredfeatures. For example, a large switch may be fabricated to achieve ONresistance values in the 50 to 100 ohm range to match the characteristicimpedance (Z_(o)) of a transmission line. Also, arrays larger thantwo-by-two, such as 100-by-100 or larger, may be formed for example.

Wire 22600-1 illustrated in FIG. 22A interconnects two terminal NV NTblock switches 22100-1 and 22100-3 by contacting top (upper level)contacts, with each of the two terminal NV NT block switches havingdimensions F×F and separated by a distance F. Wire 22600-2 interconnectstwo terminal NV NT block switches 22100-2 and 22100-4 by contacting top(upper level) contacts, with each of the two terminal NV NT blockswitches having dimensions F×F and separated by a distance F. Wires22600-1 and 22600-2 are patterned on the surface of insulator 22500 thatfills regions between NV NT block switches. While F represents minimumfeature size to achieve maximum switch array density, dimensions largerthan F may be used.

FIG. 22B illustrates cross section X1-X1′ through and along wire 22600-1in the X direction. The Z direction represents the vertical orientationof two terminal NV NT block switch 22100-1 and also indicates thedirection of current flow (vertically) in the ON state. Two terminal NVNT block switch 22100-1 includes bottom (lower level) contact 22050-1′which is a section of wire 22050-1, top (upper level) contact NV NTblock 22400-1 which is in contact with wire 22600-1, and NV NT block22200-1 which is in contact with both bottom (lower level) contact22050-1′ and top (upper level) contact 22400-1. NV NT block 22200-1 maybe switched between ON and OFF states multiple times as describedfurther above and in the incorporated patent references, e.g., U.S.patent application Ser. No. 11/280,786 and U.S. patent application Ser.No. (TBA), entitled “Nonvolatile Nanotube Diodes and NonvolatileNanotube Blocks and Systems Using Same and Methods of Making Same,”filed concurrently herewith.

FIG. 22C illustrates cross section Y1-Y1′ through and along wire 22050-1in the Y direction. The Z direction represents the vertical orientationof two terminal NV NT block switch 22100-1 and also indicates thedirection (vertically) of current flow in the ON state. Two terminal NVNT block switch 22100-1 includes bottom (lower level) contact 22050-1′which is a section of wire 22050-1, top (upper level) contact NV NTblock 22400-1 which is in contact with wire 22600-1, and NV NT block22200-1 in contact with both bottom (lower level) contact 22050-1′ andtop (upper level) contact 22400-1. NV NT block 22200-1 may be switchedbetween ON and OFF states multiple times as described further above andin the incorporated patent references. Methods of fabrication of NV NTblock switches and array interconnections are described further inincorporated patent references, e.g., U.S. patent application Ser. No.(TBA), entitled “Nonvolatile Nanotube Diodes and Nonvolatile NanotubeBlocks and Systems Using Same and Methods of Making Same,” filedconcurrently herewith.

Two terminal NV NT block switches 22100-1, 22100-2, 22100-3, and 22100-4dimensions are approximately F in the horizontal direction, and F in theapproximately orthogonal Y direction, where F is the minimumlithographically defined dimension at a particular technology node. Theminimum separation with adjacent switches is F such that two terminal NVNT block switches 22100-1, 22100-2, 22100-3, and 22100-4 may be placedon a periodicity of 2F in the X and Y directions as illustrated in FIG.22A. Individual two terminal NV NT block switches 22100-1, 22100-2,22100-3, and 22100-4 occupy an area of 1F², and 4F² when placed in anarray configuration separated from other switches by minimum distance F.Hence, individual two terminal NV NT block switches 22100-1, 22100-2,22100-3, and 22100-4 are 9× denser then two terminal switch 21000illustrated in FIG. 21. In an array configuration with individualswitches separated by F in the X and Y direction, arrays of nonvolatilenanotube switches based on two terminal NV NT block switches 22100-1,22100-2, 22100-3, and 22100-4 with a periodicity of 2F occupy an area of4F² and are 4× denser than arrays of nonvolatile nanotube switches basedon two terminal switch 21000 that in some embodiments require an area of16F². F may be scaled over a large range of dimensions. F may be 250 nmand larger; less than 100 nm, for example 45 nm and 22 nm; or less than10 nm. NV NT switches with NV NT block channel lengths L_(SW-CH) in thevertical (Z) direction defined by bottom (lower level) contact to top(upper level) contact spacing of 35 nm have been fabricated as describedin the incorporated patent references. L_(SW-CH) may range from <10 nmto greater than 250 nm.

Dimension F is determined by the technology node, 45 nm for example. NVNT block switch dimensions may be F=45 nm, for example, if nanotubefabric density (the number of nanotubes per unit area) is sufficientlyhigh to achieve desired NV NT block switch ON resistance values.However, if the NV NT block switch resistance value is too high whenusing minimum F×F switch dimensions, then dimensions larger than F maybe used to increase the number of nanotubes in NV NT block switch andthereby achieve lower NV NT block switch ON resistance values. Assumingthe CMOS driver is driving CMOS circuit capacitive inputs, then inputlevels to the next logic stage will swing rail-to-rail (between on-chipvoltage supply and reference (ground) voltage) regardless of thecombined series ON resistance values of the NV NT block switch and FETchannel. However, network RC time constant delays due to the combinationof series resistance and interconnect capacitance values may requirelimits on the ON resistance value of the NV NT block switch. Forexample, if the wiring path requires a short delay time, then the ONresistance of the NV NT block switch may be no more than 1/10^(th) ofthe NMOS and PMOS ON resistances of 1k to 10k Ohms in this example,thereby limiting the ON resistance of the NV NT block switch to aresistance range of 100 Ohms to 1k Ohms. However, if a short delay timeis not required, then in this example the ON resistance of the NV NTblock switch may be equal to (or even greater) than the NMOS and PMOS ONresistance, in this case in the range of 1k Ohms to 10k Ohms. NV NTblock switch OFF resistance is typically 1 GOhm and above, with somedevices as low as 100 MOhms as described further above and in U.S.patent application Ser. No. 11/280,786 and U.S. patent application Ser.No. (TBA), entitled “Nonvolatile Nanotube Diodes and NonvolatileNanotube Blocks and Systems Using Same and Methods of Making Same,”filed concurrently herewith.

NV NT block switches 22100-1, 22100-2, 22100-3, and 22100-4 innonvolatile switch matrix 22000 are in an as-fabricated ON state. Inoperation, these NV NT block switches are typically switched to an OFFstate. Then the application determines which of the NV NT block switchesin nonvolatile switch matrix 22000 are switched to the ON state to forminterconnected wiring.

In operation, as-fabricated ON NV NT block switches may all be switchedfrom ON to OFF simultaneously by activating all rows, or may be switchedone row at a time, or may be switched one NV NT block switch at a time.In this example, switches are switched from ON to OFF one row at a time.NV NT block switches 22100-1 and 22100-3 are switched from ON to OFF bya write 0 (also referred to as erase) operation. First, vertical wires22050-1 and 22050-2 are set to and held at a reference voltage such aszero volts (ground). Next, horizontal wire 22100-2 is set to zero andheld at zero volts and horizontal wire 22100-1 is ramped from areference voltage such as zero volts (ground) to a write 0 voltage in arange of 4 to 8 volts, for example. The ramp rate may in the 1 to 10 nsrange, or much slower, in the 100's of ns or microsecond range, forexample, with write 0 current flow per switch in the range of 1 uA to100 uA as described further above and in the incorporated patentreferences. While a 2×2 array of NV NT block switches is described inthis example, larger N×M switch matrices may be used, where N and M mayinclude hundreds, thousands, and even more NV NT block switches.

In operation, any combination of nonvolatile electrically programmableand re-programmable connections between horizontal and vertical wiresmay be realized by electrically activating (turning from an OFF state toON state) any combination of NV NT block switches using a write 1 (alsoreferred to as programming) operation, where NV NT block switch 22100-1,22100-2, 22100-3, and 22100-4 ON state determines electrical wiringconnections (routing) between vertical wires 22050-1 and 22050-2 andhorizontal wires 22600-1 and 2260-2. In this example, write 1 operationstypically write voltages in the 4 to 8 volt range. The ramp rate may inthe sub-10 ns range, or much slower, in the 100's of ns or microsecondrange, for example, with write 1 current flow per switch in the range of1 uA to 100 uA as described further in U.S. patent application Ser. No.11/280,786 and U.S. Provisional Patent Application No. 60/855,109.

By way of example, NV NT block switch 22100-1 may be in an ON stateconnecting wires 22600-1 and 22050-1 and NV NT block switch 22100-4 mayalso be in an ON state connecting wires 22600-2 and 22050-2. NV NT blockswitches 22100-2 and 22100-3 may be in the OFF state for example.Multiple wires may be connected as well. FIG. 22D illustrated furtherbelow shows various interconnections that may be formed usingnonvolatile nanotube block switch matrix 22000.

FIG. 22D illustrates nonvolatile electrically programmed wiring(routing) connections for one of four NV NT block switches in an ONstate with the remaining three switches in an OFF state. Also shown arenonvolatile electrically programmed wiring (routing) connections forpairs (two of four) NV NT block switches in an ON state with theremaining two switches in an OFF state. Selected (ON) NV NT block switchpairs may be used to form a single contact per vertical and horizontalwire pair, or multiple connections between one vertical wire and twohorizontal wires or one horizontal wire and two vertical wires asillustrated in FIG. 22D. Other NV electrically programmed wiring(routing) connections may be formed using combinations of three NV NTblock switches in an ON state with one remaining switch in an OFF state(not shown), and also all four NV NT block switches may be in the ONstate (not shown). While a 2×2 array of NV NT block switches isdescribed in this example, larger N×M switch matrices may be used, whereN and M may include hundreds, thousands, and even more NV NT blockswitches. Nonvolatile electrically programmed wiring (routing)connections may be re-programmed thousands or more times to change thewiring (routing) configuration.

In operation, after NV NT block switches have been written in an ON orOFF state, electrical signals will flow between wiring (routing) layersthrough NV NT blocks switches that are in ON state. Voltage levels arekept below write 0 and write 1 operation thresholds. In this example,electronic signals are kept below approximately four volts.

Second-Type of Dense Cross Point Switch Structures with NV NT BlockSwitches Self Aligned to Array Wiring

Nonvolatile nanotube block switch matrix 22000 is illustrated in a planview in FIG. 22A further above, and nonvolatile nanotube block switch22100-1, representative of NV NT block switches 22100-1, 22100-2,22100-3, and 22100-4, is illustrated above in cross section in FIGS. 22Band 22C and shows a first-type of NV NT block switches in which top(upper level) contact 22400-1 forms and upper level contact and also amask layer that defines the NV NT block 22200-1 etched X and Ydimensions of nonvolatile nanotube block switch 22100-1.

In another embodiment, a second-type of NV NT block switches in whichtop (upper level) contacts are eliminated and replaced instead withcombined top (upper level) contacts and array wires. For example, top(upper level) contact 22400-1 illustrated in FIGS. 22A-22C can beeliminated as illustrated further below in FIG. 23 and replaced with top(upper level) contact 23600-1′ which is a region (portion) of array wire23600-1.

FIG. 23A illustrates a plan view of nonvolatile nanotube block switchmatrix 23000 of four vertically-oriented (3-D) two terminal nonvolatilenanotube block switches (23100-1, 23100-2, 23100-3, and 23100-4) in atwo-by-two cross point switch array configuration Representative crosssections X2-X2′ and Y2-Y2′ through a portion of NV NT block switch23100-1 as illustrated in FIG. 23A further illustrate elements of NV NTblock switches in vertically-oriented (3-D) structures shown in FIGS.23B and 23C. Details of second-type two terminal NV NT block switchesand methods of fabrication, corresponding to two-terminal nonvolatilenanotube switches 23100-1, 23100-2, 23100-3, and 23100-4 are based on NVNT block switch fabrication described further in the incorporated patentreferences. However, instead of also using a top (upper level) contactas an etch mask to device NV NT block surfaces, a separate sacrificial(disposable) etch mask (not shown) in the shape of a top (upper level)contact and based on known industry patterning techniques is used todefine the X and Y dimensions of NV NT block regions, such as NV NTblock 23200-1 illustrated in FIGS. 23A-23C. NV NT block 23200-1dimensions are then defined using preferred etch methods of fabricationin the incorporated patent references to form NV NT block 23200-1 asillustrated in FIGS. 23A-23C. NV NT blocks may be deposited usingmultiple spin-on layers or by spray on techniques as described in theincorporated patent references, e.g., U.S. patent application Ser. No.(TBA), entitled “Nonvolatile Nanotube Diodes and Nonvolatile NanotubeBlocks and Systems Using Same and Methods of Making Same,” filedconcurrently herewith.

Wire 23050-1 illustrated in FIG. 23A interconnects two terminal NV NTblock switches 23100-1 and 23100-2 forming bottom (lower level)contacts, with each of these two terminal NV NT block switches havingdimensions F×F and separated by a distance F. Wire 23050-2 interconnectstwo terminal NV NT block switches 23100-3 and 23100-4, forming bottom(lower level) contacts, with each of these two terminal NV NT blockswitches having dimensions F×F and separated by a distance F. While Frepresents minimum feature size to achieve maximum switch array density,dimensions larger than F may be used as needed and non-square crosssections may be used, such as rectangular and circular for example asdescribed further above. Also, arrays larger than two-by-two, such as100-by-100 or larger, may be formed for example.

Wire 23600-1 illustrated in FIG. 23A interconnects two terminal NV NTblock switches 23100-1 and 23100-3, while also forming top (upper level)contacts such as top (upper level) contact 23600-1′, with each of thetwo terminal NV NT block switches having dimensions F×F and separated bya distance F. Wire 23600-2 interconnects two terminal NV NT blockswitches 23100-2 and 23100-4, forming top (upper level) contacts such astop (upper level) contact 23600-1′, with each of the two terminal NV NTblock switches having dimensions F×F and separated by a distance F.Wires 23600-1 and 23600-2 are patterned on the surface of insulator23500 that fills regions between two terminal NV NT block switches.While F represents minimum feature size to achieve maximum switch arraydensity, dimensions larger than F may be used as needed and non-squarecross sections may be used, such as rectangular and circular for exampleas described further above. Also, arrays larger than two-by-two, such as100-by-100 or larger, may be formed for example.

FIG. 23B illustrates cross section X2-X2′ through and along wire 23600-1in the X direction. The Z direction represents the vertical orientationof two terminal NV NT block switch 23100-1 and also indicates adirection (vertical) of current flow in the ON state. Note that currentmay flow in up or down directions. Two terminal NV NT block switch23100-1 includes bottom (lower level) contact 23050-1′ which is a regionformed by wire 23050-1, top (upper level) contact NV NT block 23600-1′which is formed by a region (portion) of wire 23600-1, and NV NT block23200-1 in contact with both bottom (lower level) contact 23050-1′ andtop (upper level) contact 23600-1′. NV NT block 23200-1 may be switchedbetween ON and OFF states multiple times as described in theincorporated patent references, e.g., U.S. patent application Ser. No.11/280,786 U.S. patent application Ser. No. (TBA), entitled “NonvolatileNanotube Diodes and Nonvolatile Nanotube Blocks and Systems Using Sameand Methods of Making Same,” filed concurrently herewith.

FIG. 23C illustrates cross section Y2-Y2′ through and along wire 23050-1in the Y direction. The Z direction represents the vertical orientationof two terminal NV NT block switch 23100-1 and also indicates adirection (vertical) of current flow in the ON state. Note that currentmay flow in up or down directions. Two terminal NV NT block switch23100-1 includes bottom (lower level) contact 23050-1′ which is a region(section) of wire 23050-1, top (upper level) contact 23600-1′ which isformed by a region (section) of wire 23600-1, and NV NT block 23200-1 incontact with both bottom (lower level) contact 23050-1′ and top (upperlevel) contact 23600-1′. NV NT block 23200-1 may be switched between ONand OFF states multiple times as described further above and in theincorporated patent references, e.g., U.S. patent application Ser. No.11/280,786 and U.S. patent application Ser. No. (TBA), entitled“Nonvolatile Nanotube Diodes and Nonvolatile Nanotube Blocks and SystemsUsing Same and Methods of Making Same,” filed concurrently herewith.

Two terminal NV NT block switches 23100-1, 23100-2, 23100-3, and 23100-4dimensions are approximately F in the horizontal direction, and F in theapproximately orthogonal Y direction, where F is the minimumlithographically defined dimension at a particular technology node. Theminimum separation with adjacent switches is F such that two terminal NVNT block switches 23100-1, 23100-2, 23100-3, and 23100-4 may be placedon a periodicity of 2F in the X and Y directions as illustrated in FIG.23A. Individual two terminal NV NT block switches 23100-1, 23100-2,23100-3, and 23100-4 occupy an area of 1F², and 4F² when placed in anarray configuration separated from other switches by minimum distance F.

In operation, the electrical switching characteristics of NV NT blockswitches 23100-1, 23100-2, 23100-3, and 23100-4 are approximately thesame as described further above with respect to switches 22100-1,22100-2, 22100-3, and 22100-4.

In operation, FIG. 22D and corresponding NV NT block switch electricalON and OFF states described further above illustrate various nonvolatileelectrically programmed wiring (routing) connections for combinations ofNV NT block switches 22100-1, 22100-2, 22100-3, and 22100-4 in NV NTblock switch array 22000 in various combinations of ON and OFF states.Combinations of NV NT block switches 23100-1, 23100-2, 23100-3, and23100-4 in NV NT block switch array 23000 correspond to thoseillustrated in FIG. 22D as described further above, except that NV NTblock switches 23100-1, 23100-2, 23100-3, and 23100-4 correspond to NVNT block switches 22100-1, 22100-2, 22100-3, and 22100-4, respectively;V-wires 23050-1 and 23050-2 correspond to V-wires 22050-1 and 22050-2,respectively; and H-wires 23600-1 and 23600-2 correspond to H-wires22600-1 and 22600-2, respectively.

INCORPORATED PATENT REFERENCES

This application is related to the following applications, the entirecontents of which are incorporated herein by reference, and which arereferred to above as the “incorporated patent references:”

U.S. patent application Ser. No. 10/128,118, now U.S. Pat. No.6,706,402, filed on Apr. 23, 2002 and entitled “Nanotube Films andArticles;”

U.S. patent application Ser. No. 10/776,572, now U.S. Pat. No.6,924,538, filed on Feb. 11, 2004 and entitled “Devices HavingVertically-Disposed Nanofabric Articles and Methods of Making the Same;”

U.S. patent application Ser. No. 10/864,186, now U.S. Pat. No.7,115,901, filed on Jun. 9, 2004 and entitled “Non-VolatileElectromechanical Field Effect Devices and Circuits Using Same andMethods of Forming Same;”

U.S. patent application Ser. No. 10/917,794, now U.S. Pat. No.7,115,960, filed on Aug. 13, 2004 and entitled “Nanotube-Based SwitchingElements;”

U.S. patent application Ser. No. 10/918,085, now U.S. Pat. No.6,990,009, filed on Aug. 13, 2004 and entitled “Nanotube-Based SwitchingElements with Multiple Controls;”

U.S. patent application Ser. No. 09/915,093, now U.S. Pat. No.6,919,592, filed on Jul. 25, 2001 and entitled “Electromechanical MemoryArray Using Nanotube Ribbons and Method for Making Same;”

U.S. patent application Ser. No. 09/915,173, now U.S. Pat. No.6,643,165, filed on Jul. 25, 2001 and entitled “Electromechanical MemoryHaving Cell Selection Circuitry Constructed With Nanotube Technology;”

U.S. patent application Ser. No. 09/915,095, now U.S. Pat. No.6,574,130, filed on Jul. 25, 2001 and entitled “Hybrid Circuit HavingNanotube Electromechanical Memory;”

U.S. patent application Ser. No. 10/033,323, now U.S. Pat. No.6,911,682, filed on Dec. 28, 2001 and entitled “ElectromechanicalThree-Trace Junction Devices;”

U.S. patent application Ser. No. 10/033,032, now U.S. Pat. No.6,784,028, filed on Dec. 28, 2001 and entitled “Methods of MakingElectromechanical Three-Trace Junction Devices;”

U.S. patent application Ser. No. 10/128,118, now U.S. Pat. No.6,706,402, filed on Apr. 23, 2002 and entitled “Nanotube Films andArticles;”

U.S. patent application Ser. No. 10/128,117, now U.S. Pat. No.6,835,591, filed Apr. 23, 2002 and entitled “Methods of Nanotube Filmsand Articles;”

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U.S. patent application Ser. No. 10/341,055, filed Jan. 13, 2003 andentitled “Methods of Using Thin Metal Layers to Make Carbon NanotubeFilms, Layers, Fabrics, Ribbons, Elements and Articles;”

U.S. patent application Ser. No. 10/341,054, filed Jan. 13, 2003 andentitled “Methods of Using Pre-formed Nanotubes to Make Carbon NanotubeFilms, Layers, Fabrics, Ribbons, Elements and Articles;”

U.S. patent application Ser. No. 10/341,130, filed Jan. 13, 2003 andentitled “Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements andArticles;”

U.S. patent application Ser. No. 10/776,059, now U.S. Patent PublicationNo. 2004/0181630, filed Feb. 11, 2004 and entitled “Devices HavingHorizontally-Disposed Nanofabric Articles and Methods of Making theSame;”

U.S. patent application Ser. No. 10/936,119, now U.S. Patent PublicationNo. 2005/0128788, filed Sep. 8, 2004 and entitled “Patterned NanoscopicArticles and Methods of Making the Same;”

U.S. Provisional Patent Application No. 60/855,109, entitled“Nonvolatile Nanotube Blocks,” filed on Oct. 27, 2006;

U.S. Provisional Patent Application No. 60/840,586, entitled“Nonvolatile Nanotube Diode,” filed on Aug. 28, 2006;

U.S. Provisional Patent Application No. 60/836,437, entitled“Nonvolatile Nanotube Diode,” filed on Aug. 8, 2006;

U.S. Provisional Patent Application No. 60/836,343, entitled “ScalableNonvolatile Nanotube Switches as Electronic Fuse Replacement Elements,”filed on Aug. 8, 2006;

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The invention may be embodied in other specific forms without departingfrom the spirit or essential characteristics thereof. The presentembodiments are therefore to be considered in respects as illustrativeand not restrictive. Atty.

1. A nanotube switch, comprising: a first and second electrodes; aswitching element having a predetermined pattern comprising a porousnetwork of nanotubes wherein at least a first nanotube is in electricalcommunication with the first electrode and at least a second nanotube isin electrical communication with the second electrode; and a protectivebarrier to protect the switching element.
 2. The nanotube switch ofclaim 1, wherein the protective barrier includes a passivation layerthat permeates at least partially into said porous network of nanotubes.3. The nanotube switch of claim 2, wherein said passivation layer is aninsulator.
 4. The nanotube switch of claim 2, wherein said passivationlayer is a conductor.
 5. The nanotube switch of claim 2, wherein saidpassivation layer is a semiconductor.
 6. The nanotube switch of claim 2,wherein said passivation layer is formed from at least one of SiO₂, SiN,Al₂O₃, and polyimide.
 7. The nanotube switch of claim 2, wherein saidpassivation layer is formed from at least one of phosphosilicate glassoxide, planarizing low temperature oxide, sputtered oxide, sputterednitride, flowfill oxide, chemical vapor deposition of oxide and nitride,atomic layer deposition oxides, and polyvinylidene fluoride.
 8. Thenanotube switch of claim 1, wherein the protective barrier seals theswitching element.
 9. The nanotube switch of claim 1, wherein theprotective barrier protects at least a portion of the switching element.10. The nanotube switch of claim 1, wherein the switching element iscapable of switching between a plurality of electronic states inresponse to electrical stimuli applied to the first and secondelectrodes.